# US 2022/0045028 A1 · Package structure and manufacturing method thereof

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- Number: US 2022/0045028 A1
- Document ID: US20220045028A1
- Status: Published application
- Kind: A1
- Application number: 17/392,274
- Filed: 2021-08-03
- Published: 2022-02-10
- Earliest claimed: 2020-08-06
- Assignees: Powertech Technology Inc.
- Applicants: Powertech Technology Inc.
- Inventors: Shang-Yu Chang Chien; Nan-Chun Lin; Hung-Hsin Hsu
- Web page: https://patentgrep.com/patent/US20220045028A1

## CPC

- H10W 72/20: Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
- H10W 90/00: Package configurations
- H10W 70/09: extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs
- H10W 72/0198: {batch processes}
- H10W 90/293: {characterised by non-galvanic coupling between the chips, e.g. capacitive coupling}
- H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
- H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40)
- H10W 70/614: {the multiple chips being integrally enclosed}
- H10W 70/6528: {of the portions that connect to chips, wafers or package parts}
- H10W 72/072: {of bump connectors}
- H10W 72/07236: {Soldering or alloying}
- H10W 72/073: {of die-attach connectors}
- H10W 72/07302: {using an auxiliary member}
- H10W 72/241: {Dispositions, e.g. layouts}
- H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu}
- H10W 72/353: {not comprising solid metals or solid metalloids, e.g. ceramics}
- H10W 72/381: {Auxiliary members}
- H10W 72/387: {Flow barriers}
- H10W 72/853: {On the same surface}
- H10W 72/9413: {on encapsulations}
- H10W 72/944: {Dispositions of multiple bond pads}
- H10W 72/951: {Materials of bond pads}
- H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills
- H10W 90/20: Configurations of stacked chips
- H10W 90/22: the stacked chips being on both top and bottom sides of a package substrate, interposer or RDL
- H10W 90/297: {characterised by the through-semiconductor vias [TSVs] in the stacked chips}
- H10W 90/722: {between stacked chips}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/732: {between stacked chips}
- H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A packaging structure including first, second, and third dies, an encapsulant, a circuit structure, and a filler is provided. The encapsulant covers the first die. The circuit structure is disposed on the encapsulant. The second die is disposed on the circuit structure and is electrically connected to the circuit structure. The third die is disposed on the circuit structure and is electrically connected to the circuit structure. The third die has an optical signal transmission area. The filler is disposed between the second die and the circuit structure and between the third die and the circuit structure. A groove is present on an upper surface of the circuit structure. The upper surface includes first and second areas located on opposite sides of the groove. The filler directly contacts the first area. The filler is away from the second area. A manufacturing method of a packaging structure is also provided.

## Claims

### Claim 1

A packaging structure, comprising:
a first die, comprising a silicon substrate and a through silicon conductor penetrating the silicon substrate;
an encapsulant, covering the first die;
a redistribution circuit structure, located on the encapsulant;
a second die, disposed on the redistribution circuit structure and electrically connected to the redistribution circuit structure;
a third die, disposed on the redistribution circuit structure and electrically connected to the redistribution circuit structure, wherein the third die has an optical signal transmission area; and
a filler, located between the second die and the redistribution circuit structure and between the third die and the redistribution circuit structure, wherein:
a groove is present on an upper surface of the redistribution circuit structure, and the upper surface comprises a first area and a second area located on opposite sides of the groove;
the filler directly contacts the first area; and
the filler is away from the second area.

### Claim 2 (depends on 1)

The packaging structure as described in claim 1, wherein the redistribution circuit structure is located on an encapsulant surface of the encapsulant, and the optical signal transmission area of the third die does not overlap the encapsulant in a direction perpendicular to the encapsulant surface.

### Claim 3 (depends on 1)

The packaging structure as described in claim 1, wherein the filler further covers a part of a side surface of the third die.

### Claim 4 (depends on 1)

The packaging structure as described in claim 1, wherein the filler is further filled into the groove.

### Claim 5 (depends on 1)

The packaging structure as described in claim 1, wherein the groove is in a stripe shape, and in an extension direction of the groove, a dimension of the groove is greater than a dimension of the third die, and the dimension of the groove is less than a dimension of the encapsulant.

### Claim 6 (depends on 1)

The packaging structure as described in claim 1, further comprising:
a plurality of third die connectors, located between the third die and the redistribution circuit structure and electrically connected to the third die and the redistribution circuit structure, wherein the groove is in an annular shape and encloses the plurality of third die connectors.

### Claim 7 (depends on 1)

The packaging structure as described in claim 1, wherein the redistribution circuit structure comprises:
a top insulating layer, wherein the groove penetrates the top insulating layer; and
a top conductive layer, located on the top insulating layer, wherein a part of the top conductive layer is further embedded in the top insulating layer.

### Claim 8 (depends on 1)

The packaging structure as described in claim 1, wherein a side wall of the groove is an inclined plane.

### Claim 9 (depends on 8)

The packaging structure as described in claim 8, wherein the redistribution circuit structure comprises a dummy pad, and the groove exposes a surface of the dummy pad.

### Claim 10 (depends on 1)

The packaging structure as described in claim 1, wherein a side wall of the groove has a step structure.

### Claim 11

A manufacturing method of a packaging structure, comprising:
providing a preliminary structure, comprising:
a first die, comprising a silicon substrate and a through silicon conductor penetrating the silicon substrate;
an encapsulant, covering the first die; and
a redistribution circuit structure, located on the encapsulant and electrically connected to the first die, wherein a groove is present on an upper surface of the redistribution circuit structure, and the upper surface comprises a first area and a second area located on opposite sides of the groove;
disposing a second die on the preliminary structure, and electrically connecting the second die to the redistribution circuit structure;
disposing a third die on the preliminary structure, and electrically connecting the third die to the redistribution circuit structure, wherein the third die has an optical signal transmission area; and
forming a filler between the second die and the redistribution circuit structure and between the third die and the redistribution circuit structure, wherein the filler directly contacts the first area, and the filler is away from the second area.

### Claim 12 (depends on 11)

The manufacturing method as described in claim 11, wherein forming the redistribution circuit structure of the preliminary structure comprises:
forming a top insulating material layer; and
removing a part of the top insulating material layer to form the groove.

### Claim 13 (depends on 12)

The manufacturing method as described in claim 12, wherein forming the redistribution circuit structure of the preliminary structure further comprises:
forming the top insulating material layer on a dummy pad; and
removing a part of the top insulating material layer to expose the dummy pad to form the groove.

### Claim 14 (depends on 12)

The manufacturing method as described in claim 12, wherein forming the redistribution circuit structure of the preliminary structure further comprises:
forming an insulating layer, wherein an insulating opening is present in the insulating layer;
forming the top insulating material layer on the insulating layer and further filling the top insulating material layer into the insulating opening; and
removing a part of the top insulating material layer located in the insulating opening and corresponding to the insulating opening to form the groove.

### Claim 15 (depends on 12)

The manufacturing method as described in claim 12, further comprising:
after forming the groove, performing a step of cutting to form a plurality of preliminary structures.