# US 2022/0045027 A1 · Semiconductor device and method of manufacturing the same

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- Number: US 2022/0045027 A1
- Document ID: US20220045027A1
- Status: Published application
- Kind: A1
- Application number: 17/365,044
- Filed: 2021-07-01
- Published: 2022-02-10
- Earliest claimed: 2020-08-04
- Assignees: Panasonic Intellectual Property Management Co., Ltd.
- Applicants: Panasonic Intellectual Property Management Co., Ltd.
- Inventors: SHOZO OCHI; HIDETOSHI KITAURA
- Web page: https://patentgrep.com/patent/US20220045027A1

## CPC

- H10W 72/30: Die-attach connectors
- H10W 72/013: {of die-attach connectors}
- H10W 72/073: {of die-attach connectors}
- H10W 40/255: {having a laminate or multilayered structure, e.g. direct bond copper [DBC] ceramic substrates}
- H10W 72/01325: {in solid form}
- H10W 72/01351: {Changing the shapes of die-attach connectors}
- H10W 72/01361: {Chemical or physical modification, e.g. by sintering or anodisation (patterning H10W72/01351)}
- H10W 72/07331: {Connecting techniques}
- H10W 72/07353: {changes in shapes}
- H10W 72/322: {Multilayered die-attach connectors, e.g. a coating on a top surface of a core}
- H10W 72/325: {Die-attach connectors having a filler embedded in a matrix}
- H10W 72/334: {Cross-sectional shape, i.e. in side view}
- H10W 72/352: {comprising metals or metalloids, e.g. solders}
- H10W 72/353: {not comprising solid metals or solid metalloids, e.g. ceramics}
- H10W 72/952: {comprising metals or metalloids, e.g. PbSn, Ag or Cu}
- H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor device includes an insulation board, an electrode provided on the insulation board, a bonding layer provided on the electrode and made of a sintered body of metal particles having an average particle size of nano-order, and a semiconductor element bonded to the electrode via the bonding layer. A layer thickness of the bonding layer is greater than or equal to 220 μm and less than or equal to 700 μm.

## Claims

### Claim 1

A semiconductor device comprising:
an insulation board;
an electrode provided on the insulation board;
a bonding layer provided on the electrode and made of a sintered body of metal particles having an average particle size of nano-order; and
a semiconductor element bonded to the electrode via the bonding layer,
wherein a layer thickness of the bonding layer is greater than or equal to 220 μm and less than or equal to 700 μm.

### Claim 2 (depends on 1)

The semiconductor device of claim 1,
wherein a side surface of the bonding layer has a stair-like step in cross-sectional view.

### Claim 3 (depends on 1)

The semiconductor device of claim 1,
wherein the bonding layer includes
a first bonding layer provided on the electrode,
a second bonding layer provided on the first bonding layer, and
a third bonding layer provided on the second bonding layer, and
a layer thickness of the second bonding layer is larger than a layer thickness of each of the first bonding layer and the third bonding layer.

### Claim 4 (depends on 3)

The semiconductor device of claim 3,
wherein the layer thickness of the second bonding layer is greater than or equal to 200 μm and less than or equal to 500 μm.

### Claim 5 (depends on 3)

The semiconductor device of claim 3,
wherein the layer thickness of each of the first bonding layer and the third bonding layer is greater than or equal to 10 μm and less than or equal to 100 μm.

### Claim 6 (depends on 3)

The semiconductor device of claim 3,
wherein areas of the first bonding layer, the second bonding layer, and the third bonding layer in plane view satisfy the following expression,
area of first bonding layer≥area of second bonding layer≥area of third bonding layer.

### Claim 7 (depends on 6)

The semiconductor device of claim 6,
wherein side surfaces of the first bonding layer, the second bonding layer, and the third bonding layer have stair-like steps in cross-sectional view.

### Claim 8 (depends on 1)

The semiconductor device of claim 1,
wherein the average particle size of the metal particles is greater than or equal to 10 nm and less than or equal to 100 nm.

### Claim 9 (depends on 1)

The semiconductor device of claim 1,
wherein a material of the metal particles is Ag.

### Claim 10 (depends on 1)

The semiconductor device of claim 1,
wherein a material of the electrode is Cu or Al.

### Claim 11 (depends on 1)

The semiconductor device of claim 1,
wherein a metal layer including a material different from a metal material of the electrode is provided on the electrode, and the material of the metal layer is any of Au, Pt, Pd, Ag, Cu, Ti and Ni.

### Claim 12 (depends on 1)

The semiconductor device of claim 1,
wherein a material of the semiconductor element is any of silicon carbide, gallium nitride, gallium arsenide and diamond.

### Claim 13

A method of manufacturing a semiconductor device, comprising:
printing a first sinter bonding material containing metal nanoparticles on an electrode bonded to an insulation board;
placing a second bonding layer made of a sintered body of metal particles having an average particle size of nano-order on the first sinter bonding material;
printing a third sinter bonding material containing metal nanoparticles on the second bonding layer;
placing a semiconductor element on the third sinter bonding material; and
sintering the first sinter bonding material and the third sinter bonding material by heating while pressurizing after the semiconductor element is placed, forming a sinter bonding layer including the second bonding layer, and then bonding the electrode and the semiconductor element via the sinter bonding layer.

### Claim 14 (depends on 13)

The method of manufacturing the semiconductor device of claim 13,
wherein the second bonding layer is prepared in advance by a method including:
preparing a support base;
applying a first mold release agent on the support base and drying;
applying a second mold release agent on the first mold release agent and drying;
printing a second sinter bonding material containing metal nanoparticles on the second mold release agent;
forming a second bonding layer by heating and sintering the second sinter bonding material; and
releasing the second bonding layer from the support base.