# US 2022/0045025 A1 · Semiconductor package structure and manufacturing method thereof

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- Number: US 2022/0045025 A1
- Document ID: US20220045025A1
- Status: Published application
- Kind: A1
- Application number: 17/385,991
- Filed: 2021-07-27
- Published: 2022-02-10
- Earliest claimed: 2020-08-04
- Assignees: Phoenix Pioneer Technology Co., Ltd.
- Applicants: Phoenix Pioneer Technology Co., Ltd.
- Inventors: Che-Wei Hsu
- Web page: https://patentgrep.com/patent/US20220045025A1

## CPC

- H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40)
- H10W 70/09: extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs
- H10W 70/614: {the multiple chips being integrally enclosed}
- H10W 90/00: Package configurations
- H10W 70/099: {Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers}
- H10W 70/424: {Cross-sectional shapes (H10W70/481 takes precedence)}
- H10W 70/466: {Tape carriers or flat leads}
- H10W 70/481: {for devices being provided for in groups H10D8/00 - H10D48/00}
- H10W 70/63: Vias, e.g. via plugs
- H10W 70/6528: {of the portions that connect to chips, wafers or package parts}
- H10W 72/072: {of bump connectors}
- H10W 72/073: {of die-attach connectors}
- H10W 72/241: {Dispositions, e.g. layouts}
- H10W 72/874: {On different surfaces}
- H10W 72/926: {Multiple bond pads having different sizes}
- H10W 72/9413: {on encapsulations}
- H10W 72/944: {Dispositions of multiple bond pads}
- H10W 90/10: Configurations of laterally-adjacent chips
- H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts}
- H10W 90/722: {between stacked chips}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/736: {between a chip and a stacked lead frame, conducting package substrate or heat sink}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

The present invention provides a semiconductor package structure including a first dielectric layer, an integrated chip, a second power chip, a first patterned conductive layer, a second patterned conductive layer, a first conductive adhesive part, a second conductive adhesive part, a plurality of first conductive connecting elements and a plurality of second conductive connecting elements, and including a build-up circuit structure below, wherein the integrated chip includes a control chip and a first power chip. By means of integrating the control chip and the first power chip into a single chip, volume of semiconductor package structure can be further reduced. In addition, a manufacturing method of a semiconductor package structure is also provided.

## Claims

### Claim 1

A semiconductor package structure, comprising:
a first dielectric layer, which has a first surface and a second surface arranged opposite to each other;
a first patterned conductive layer, which is disposed on the second surface of the first dielectric layer;
an integrated chip, which is embedded in the first dielectric layer, comprising:
a control chip, which has an active surface and a rear surface, and the rear surface being facing the second surface of the first dielectric layer; and
a first power chip, which is a High-Side MOSFET and has a first front surface with a first electrode layout and a first rear surface with a second electrode layout, wherein the first power chip is electrically connected and adhered to the first patterned conductive layer through a first conductive adhesive part by the second electrode layout;
a second power chip, which is a Low-Side MOSFET embedded in the first dielectric layer, and has a second front surface with a third electrode layout and a second rear surface with a fourth electrode layout, wherein the second power chip is electrically connected and adhered to the first patterned conductive layer through a second conductive adhesive part by the fourth electrode layout;
a second patterned conductive layer, which is disposed on the first surface of the first dielectric layer and is electrically connected to the first electrode layout of the first power chip and the third electrode layout of the second power chip through a plurality of first conductive connecting elements;
a plurality of second conductive connecting elements, which are electrically connected between the first patterned conductive layer and the second patterned conductive layer; and
a build-up circuit structure, which is disposed on the first surface of the first dielectric layer and is electrically connected to the second patterned conductive layer.

### Claim 2 (depends on 1)

The semiconductor package structure of claim 1, wherein the first electrode layout of the first power chip is the same as the third electrode layout of the second power chip and includes a gate and a source respectively, and the second electrode layout of the first power chip is the same as the fourth electrode layout of the second power chip and includes a drain respectively.

### Claim 3 (depends on 2)

The semiconductor package structure of claim 2, wherein the source of the first power chip is electrically connected to the drain of the drain of the second power chip via one of the first conductive connecting elements, the second patterned conductive layer, one of the second conductive connecting elements, the first patterned conductive layer and the first conductive adhesive part.

### Claim 4 (depends on 1)

The semiconductor package structure of claim 1, wherein the first electrode layout of the first power chip is the same as the fourth electrode layout of the second power chip and includes a gate and a source respectively, and the second electrode layout of the first power chip is the same as the third electrode layout of the second power chip and includes a drain respectively.

### Claim 5 (depends on 4)

The semiconductor package structure of claim 4, wherein the source of the first power chip is electrically connected to the drain of the second power chip through two of the first conductive connecting elements and the second patterned conductive layer.

### Claim 6 (depends on 1)

The semiconductor package structure of claim 1, wherein the control chip is a driver chip and the active surface is provided with at least one connecting pad, and the second patterned conductive layer is electrically connected to the connecting pad via one of the first conductive connecting elements.

### Claim 7 (depends on 1)

The semiconductor package structure of claim 1, wherein the build-up circuit structure comprising:
a second dielectric layer, which has a third surface and a fourth surface arranged opposite to each other, and is connected to the first surface of the first dielectric layer by the fourth surface; and
a third patterned conductive layer, which is disposed on the third surface of the second dielectric layer and is electrically connected to the second patterned conductive layer through a plurality of third conductive connecting elements.

### Claim 8

A manufacturing method of semiconductor package structure, comprising:
providing a carrier board;
forming a first patterned conductive layer on the carrier board;
disposing an integrated chip on the first patterned conductive layer via a first conductive adhesive part, wherein the integrated chip including a control chip and a first power chip, and the first power chip is a High-Side MOSFET;
disposing a second power chip on the first patterned conductive layer via a second conductive adhesive part, wherein the second power chip is a Low-Side MOSFET;
forming a plurality of second conductive connecting elements on the first patterned conductive layer;
forming a first dielectric layer having a first surface and a second surface to cover the first patterned conductive layer, the first conductive adhesive part, the second conductive adhesive part, the integrated chip, the second power chip and the second conductive connecting elements, wherein a second surface of the first dielectric layer is temporarily connected to the carrier board;
forming a plurality of first conductive connecting elements to electrically connected to an active surface of the control chip, a first electrode layout of the first power chip and a third electrode layout of the second power chip;
forming a second patterned conductive layer on a first surface of the first dielectric layer, and electrically connected to the first conductive connecting elements and the second conductive connecting elements;
forming a build-up circuit structure on the first surface of the first dielectric layer, and electrically connected to the second patterned conductive layer; and
removing the carrier board.

### Claim 9 (depends on 8)

The manufacturing method of claim 8, wherein a rear surface of the control chip and a second electrode layout of the first power chip are fixed to the first conductive adhesive part, and a fourth electrode layout of the second power chip is fixed to the second conductive adhesive part, wherein the second electrode layout of the first power chip is the same as the fourth electrode layout of the second power chip and being including a drain, respectively.

### Claim 10 (depends on 9)

The manufacturing method of claim 9, wherein the first electrode layout of the first power chip is the same as the third electrode layout of the second power chip and includes a gate and a source, respectively, and the source of the first power chip is electrically connected to the drain of the second power chip via one of the first conductive connecting elements, the second patterned conductive layer, one of the second conductive connecting elements, the first patterned conductive layer and the first conductive adhesive part.

### Claim 11 (depends on 8)

The manufacturing method of claim 8, wherein a rear surface of the control chip and a second electrode layout of the first power chip include a drain, which are fixed to the first conductive adhesive part, and a fourth electrode layout of the second power chip includes a gate and a source, which are fixed to the second conductive adhesive part which is electrically separated.

### Claim 12 (depends on 11)

The manufacturing method of claim 11, wherein the first electrode layout of the first power chip includes a gate and a source, the third electrode layout of the second power chip includes a drain, and the source of the first power chip is electrically connected to the drain of the second power chip via two of the first conductive connecting elements and the second patterned conductive layer.

### Claim 13 (depends on 8)

The manufacturing method of claim 8, further comprising:
forming a plurality of first openings in the first dielectric layer to expose the active surface of the control chip, the first electrode layout of the first power chip and the third electrode layout of the second power chip, wherein the first conductive connecting elements are formed in the first openings.

### Claim 14 (depends on 13)

The manufacturing method of claim 13, wherein the first conductive connecting elements and the second patterned conductive layer are formed simultaneously in the same process.

### Claim 15 (depends on 8)

The manufacturing method of claim 8, wherein before the step of disposing the integrated chip and the second power chip on the first patterned conductive layer, the first conductive connecting elements are pre-shaped on the active surface of the control chip, the first electrode layout of the first power chip and the third electrode layout of the second power chip.

### Claim 16 (depends on 8)

The manufacturing method of claim 8, the steps to form the build-up circuit structure comprising:
forming a plurality of third conductive connecting elements on the second patterned conductive layer;
forming a second dielectric layer, which has a third surface and a fourth surface opposite to each other to cover the third conductive connecting elements and the second patterned conductive layer, wherein the fourth surface of the second dielectric layer is connected to the first surface of the first dielectric layer; and
forming a third patterned conductive layer on the third surface of the second dielectric layer, so that the third patterned conductive layer is electrically connected to the third conductive connecting elements.