# US 2022/0045020 A1 · Chip protected against back-face attacks

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- Number: US 2022/0045020 A1
- Document ID: US20220045020A1
- Status: Published application
- Kind: A1
- Application number: 17/451,718
- Filed: 2021-10-21
- Published: 2022-02-10
- Earliest claimed: 2016-08-31
- Assignees: STMicroelectronics (Crolles 2) SAS
- Applicants: STMicroelectronics (Crolles 2) SAS
- Inventors: Sebastien Petitdidier; Nicolas Hotellier; Raul Andres Bianchi; Alexis Farcy; Benoit Froment
- Web page: https://patentgrep.com/patent/US20220045020A1

## CPC

- H10W 42/405: {using active circuits}
- H03K 3/3565: Bistables with hysteresis, e.g. Schmitt trigger
- H10P 50/283: {by chemical means}
- H10W 20/023: {the interconnections being through-semiconductor vias}
- H10W 20/0234: {comprising etching via holes that stop on pads or on electrodes}
- H10W 20/0242: {comprising etching via holes from the back sides of the chips, wafers or substrates}
- H10W 20/0265: {characterised by the sidewall insulation}
- H10W 20/056: {by filling conductive material into holes, grooves or trenches}
- H10W 20/076: {in via holes or trenches}
- H10W 20/081: {by forming openings in the dielectric parts}
- H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
- H10W 20/42: Vias, e.g. via plugs
- H10W 20/43: Layouts of interconnections
- H10W 42/00: Arrangements for protection of devices (arrangements for thermal protection H10W40/00)
- H10W 42/40: protecting against tampering, e.g. unauthorised inspection or reverse engineering
- H10W 44/601: {Capacitive arrangements (H10W44/20 takes precedence)}
- H10W 70/699: {for flat cards, e.g. credit cards}
- H10W 74/137: {the encapsulations being directly on the semiconductor body (H10W74/134 takes precedence)}
- H10W 74/43: comprising oxides, nitrides or carbides, e.g. ceramics or glasses
- H10W 74/47: comprising organic materials, e.g. plastics or resins
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A method for fabricating a semiconductor chip includes forming a plurality of conducting pads at a front face of a substrate, thinning a rear face of the substrate, etching openings under each conducting pad from the rear face, depositing a layer of a dielectric on walls and a bottom of the openings, forming a conducting material in the openings, and forming a conducting strip on the rear face. The conducting strip is electrically connected to the conducting material of each of the openings. The etching is stopped when the respective conducting pad is reached.

## Claims

### Claim 1

A method for fabricating a semiconductor chip, the method comprising:
forming a plurality of conducting pads at a front face of a substrate;
thinning a rear face of the substrate;
etching openings under each conducting pad from the rear face, the etching stopping when the respective conducting pad is reached;
depositing a layer of a dielectric on walls and a bottom of the openings;
forming a conducting material in the openings; and
forming a conducting strip on the rear face, the conducting strip electrically connected to the conducting material of each of the openings.

### Claim 2 (depends on 1)

The method according to claim 1, wherein each conducting pad is an N-type doped region.

### Claim 3 (depends on 2)

The method according to claim 2, wherein each N-type doped region has a height between about 1 μm and about 10 μm.

### Claim 4 (depends on 1)

The method according to claim 1, wherein the etching includes etching further openings under further conducting pads:
wherein the depositing includes depositing the layer of the dielectric on walls and a bottom of the further openings;
wherein forming the conducting material includes forming conducting material in the further openings; and
wherein the method further comprises forming a second conducting strip on the rear face, the second conducting strip electrically connected to the conducting material of each of the further openings.

### Claim 5 (depends on 1)

The method according to claim 1, further comprising uniformly covering the rear face of the substrate with an insulating material.

### Claim 6

A method for fabricating a semiconductor chip, the method comprising:
forming a first plurality of conducting pads at a front face of a substrate;
etching a rear face of the substrate to form a first plurality of openings under each of the first plurality of conducting pads, each of the first plurality of openings comprising walls and a bottom;
depositing a layer of dielectric on the walls and the bottom of each of the first plurality of openings; and
forming a first conductive region at the rear face in each of the first plurality of openings, the first conductive region being electrically connected to each of the first plurality of conducting pads.

### Claim 7 (depends on 6)

The method according to claim 6, wherein each of the first plurality of conducting pads is an N-type doped region.

### Claim 8 (depends on 7)

The method according to claim 7, wherein each N-type doped region has a height between about 1 μm and about 10 μm.

### Claim 9 (depends on 6)

The method according to claim 6, further comprising:
uniformly covering the rear face of the substrate with an insulating material.

### Claim 10 (depends on 6)

The method according to claim 6, further comprising:
thinning the rear face of the substrate prior to etching the rear face of the substrate to form the first plurality of openings.

### Claim 11 (depends on 6)

The method according to claim 6, further comprising:
forming shallow trench isolation regions in the substrate at the front face of the substrate prior to forming the first plurality of conducting pads, wherein each of the shallow trench isolation regions is under a corresponding conducting pad of the first plurality of conducting pads.

### Claim 12

The method according to claim ii, wherein etching the rear face of the substrate to form the first plurality of openings comprises at least partially etching the shallow trench isolation regions.

### Claim 13 (depends on 6)

The method according to claim 6, wherein forming the first conductive region comprises:
forming a conducting material in each of the first plurality of openings; and
forming a conducting strip on the rear face, the conducting strip electrically connected to the conducting material of each of the first plurality of openings.

### Claim 14 (depends on 6)

The method according to claim 6, further comprising:
forming a second plurality of conducting pads at the front face of the substrate;
etching the rear face of the substrate to form a second plurality of openings under each of the second plurality of conducting pads, each of the second plurality of openings comprising walls and a bottom,
wherein depositing the layer of dielectric comprises depositing the layer of dielectric on the walls and the bottom of each of the second plurality of openings; and
forming a second conductive region at the rear face in each of the second plurality of openings, the second conductive region being electrically connected to each of the second plurality of conducting pads.

### Claim 15 (depends on 6)

The method according to claim 6, further comprising:
forming one or more additional conducting pads at the front face of the substrate, wherein no openings of the first plurality of openings are formed under any of the one or more additional conducting pads.

### Claim 16 (depends on 6)

The method according to claim 6, further comprising:
etching the rear face of the substrate to form one or more additional openings not under any of the first plurality of conducting pads, each of the one or more additional openings comprising walls and a bottom,
wherein depositing the layer of dielectric comprises depositing the layer of dielectric on the walls and the bottom of each of the one or more additional openings,
wherein forming the first conductive region comprises forming the first conductive region at the rear face in each of the one or more additional openings.

### Claim 17

A method of determining whether a hack attempt is made on an electronic chip that includes a first and second conducting pads at a front face that are capacitively coupled by a conducting strip at a rear face opposite the front face, the method comprising:
measuring a capacitance between the first conducting pad and the second conducting pad;
determining the existence of a hack attempt when the measured capacitance is higher than a threshold capacitance value; and
determining the absence of a hack attempt when the measured capacitance is lower than the threshold capacitance value.

### Claim 18 (depends on 17)

The method according to claim 17, wherein the electronic chip includes circuitry disposed at the front face, the circuitry configured to store or process confidential information.

### Claim 19 (depends on 17)

The method according to claim 17, wherein the electronic chip includes first and second insulated vias extending between the front face and the rear face of the electronic chip, wherein the first insulated via is separated from the first conducting pad by a first region of dielectric and the second insulated via is separated from the second conducting pad by a second region of dielectric.

### Claim 20 (depends on 17)

The method according to claim 17, wherein measuring the capacitance comprises using a circuit comprising an inverter with an input and an output that is coupled to the first conducting pad and a Schmitt-trigger flip-flop with an input coupled to the first conducting pad and an output coupled to the input of the inverter.