# US 2022/0045015 A1 · Nand flash block architecture enhancement to prevent block lifting

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- Number: US 2022/0045015 A1
- Document ID: US20220045015A1
- Status: Published application
- Kind: A1
- Application number: 16/984,962
- Filed: 2020-08-04
- Published: 2022-02-10
- Earliest claimed: 2020-08-04
- Assignees: Micron Technology, Inc.
- Applicants: Micron Technology, Inc.
- Inventors: Martin Jared Barclay; Mark Tunik
- Web page: https://patentgrep.com/patent/US20220045015A1

## CPC

- H10W 42/121: {protecting against mechanical damage (H10W76/00, H10W74/00 take precedence)}
- H10B 20/00: Read-only memory [ROM] devices
- H10B 41/10: characterised by the top-view layout
- H10B 41/27: the channels comprising vertical portions, e.g. U-shaped channels
- H10B 41/50: characterised by the boundary region between the core region and the peripheral circuit region
- H10B 43/10: characterised by the top-view layout
- H10B 43/27: the channels comprising vertical portions, e.g. U-shaped channels
- H10B 43/50: characterised by the boundary region between the core and peripheral circuit regions
- H10W 20/062: {by smoothing of conductive parts, e.g. by planarisation}
- H10W 20/0698: {Local interconnections}
- H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10B: ELECTRONIC MEMORY DEVICES

## Abstract

Disclosed is a three-dimensional memory device. In one embodiment, a device is disclosed comprising a source plate; plugs fabricated fabricated on or partially formed in the source plate; a stack formed on the substrate and plugs comprising alternating insulating layers and conductive layers and channel-material strings of memory cells extending through the insulating layers and conductive layers; a first set of pillars extending through the stack formed by a process including etching the alternating insulating layers and conductive layers and depositing a pillar material therein, wherein each pillar in the first set of pillars terminates atop a respective plug in the plurality of plugs; and a second set of pillars extending through the stack formed by a process including etching the alternating insulating layers and conductive layers and depositing a pillar material therein, wherein each pillar in the second set of pillars terminates in the source plate.

## Claims

### Claim 1

A semiconductor device comprising:
a source plate;
a plurality of plugs fabricated fabricated on, or at least formed partly in, the source plate;
a stack formed on the substrate and plurality of plugs, the stack comprising alternating insulating layers and conductive layers;
a first set of pillars extending through the stack formed by a process including etching the alternating insulating layers and conductive layers and depositing a pillar material therein, wherein each pillar in the first set of pillars terminates atop a respective plug in the plurality of plugs and forms a channel-material string of memory cells extending through the insulating layers and conductive layers; and
a second set of pillars extending through the stack formed by a process including etching the alternating insulating layers and conductive layers and depositing a pillar material therein, wherein each pillar in the second set of pillars terminates in the source plate.

### Claim 2 (depends on 1)

The device of claim 1, wherein the source plate comprises a silicon substrate.

### Claim 3 (depends on 2)

The device of claim 2, wherein the source plate further comprises one or more layers forming a source gate.

### Claim 4 (depends on 3)

The device of claim 3, wherein the source gate conductively contacts each of the first set of pillars.

### Claim 5 (depends on 4)

The device of claim 4, wherein the source gate does not conductively contact any of the second set of pillars.

### Claim 6 (depends on 1)

The device of claim 1, wherein the plurality of plugs comprises a plurality of tungsten plugs.

### Claim 7 (depends on 1)

The device of claim 1, wherein the insulating material comprises silicon nitride and the conductive material comprises silicon oxide.

### Claim 8

A method of making a semiconductor device, comprising:
depositing a layer of silicon oxide on a source plate;
depositing a photoresist layer on the layer of silicon oxide;
forming a plurality of holes in the layer of silicon oxide via a mask pattern placed on top of the photoresist layer, the plurality of holes formed on, or at least formed partly in, the source plate;
depositing a layer of conductive material in the plurality of holes;
depositing a stack on the layer of silicon oxide and plurality of holes, the stack comprising alternating insulating layers and conductive layers;
forming a first set of pillars on the plugs by etching the alternating insulating layers and conductive layers and depositing a pillar material therein; and
forming second set of pillars in the source plate by by etching the alternating insulating layers and conductive layers and depositing a pillar material therein.

### Claim 9 (depends on 8)

The method of claim 8, wherein the source plate is fabricated by:
depositing a layer of tungsten silicide (WSix) on a silicon substrate;
depositing a layer of polysilicon on the layer of WSix;
depositing a photoresist on the layer of polysilicon;
forming a plurality of source lines in the source plate via dry or wet etching.

### Claim 10 (depends on 8)

The method of claim 8, wherein the layer of silicon oxide is deposited via tetraethyl orthosilicate (TEOS) deposition.

### Claim 11 (depends on 8)

The method of claim 8, the photoresist layer comprising a photopolymeric, photodecomposing, or photocrosslinking photoresist layer.

### Claim 12 (depends on 8)

The method of claim 8, wherein the plurality of holes are formed below channel-material strings of memory cells extending through the insulating layers and conductive layers.

### Claim 13 (depends on 8)

The method of claim 8, the conductive material comprising tungsten.

### Claim 14 (depends on 13)

The method of claim 13, further comprising applying a tungsten plug chemical mechanical polishing (WCMP) after depositing the layer of tungsten.

### Claim 15 (depends on 8)

The method of claim 8, wherein forming the first and second set of pillars comprises depositing a hard mark on the stack, the hard mask comprising a pillar pattern defining the first and second set of pillars

### Claim 16 (depends on 15)

The method of claim 15, wherein etching the first and second set of pillars comprises performing a high-aspect ratio etch through the stack.

### Claim 17 (depends on 1)

The method of claim 1, further comprising removing the insulating layers of the stack depositing tungsten on the conductive layers tungsten via an inside-out tungsten deposition process.

### Claim 18 (depends on 1)

The method of claim 1, further comprising depositing a polysilicon coating in the first and second set of pillars.

### Claim 19 (depends on 17)

The method of claim 17, further comprising depositing silicon dioxide on the polysilicon coating.

### Claim 20 (depends on 1)

The method of claim 1, wherein the insulating layer comprises silicon nitride and the conductive layer comprises silicon oxide.