# US 2022/0045009 A1 · Semiconductor device having wafer-to-wafer bonding structure and manufacturing method thereof

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- Number: US 2022/0045009 A1
- Document ID: US20220045009A1
- Status: Published application
- Kind: A1
- Application number: 17/148,147
- Filed: 2021-01-13
- Published: 2022-02-10
- Earliest claimed: 2020-08-04
- Assignees: SK hynix Inc.
- Applicants: SK hynix Inc.
- Inventors: Sung Lae OH
- Web page: https://patentgrep.com/patent/US20220045009A1

## CPC

- H10W 20/023: {the interconnections being through-semiconductor vias}
- H10W 70/611: {for connecting multiple chips together}
- H10B 43/27: the channels comprising vertical portions, e.g. U-shaped channels
- H10D 62/115: {Dielectric isolations, e.g. air gaps}
- H10D 88/00: Three-dimensional [3D] integrated devices
- H10W 10/011: {of isolation regions comprising dielectric materials}
- H10W 10/10: Isolation regions comprising dielectric materials
- H10W 20/0234: {comprising etching via holes that stop on pads or on electrodes}
- H10W 20/0265: {characterised by the sidewall insulation}
- H10W 20/081: {by forming openings in the dielectric parts}
- H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
- H10W 20/212: {Top-view shapes or dispositions, e.g. top-view layouts of the vias}
- H10W 20/2134: {TSVs extending from the semiconductor wafer into back-end-of-line layers}
- H10W 70/635: {Through-vias}
- H10W 70/65: Shapes or dispositions of interconnections
- H10W 80/00: Direct bonding of chips, wafers or substrates
- H10W 90/00: Package configurations
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 88/01: {Manufacture or treatment}
- H10P 90/1914: {using bonding}
- H10W 10/014: {using trench refilling with dielectric materials, e.g. shallow trench isolations}
- H10W 10/17: formed using trench refilling with dielectric materials, e.g. shallow trench isolations
- H10W 90/297: {characterised by the through-semiconductor vias [TSVs] in the stacked chips}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10B: ELECTRONIC MEMORY DEVICES
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor device includes a lower wafer including a first substrate, a first dielectric layer that is defined on the first substrate, and a first wiring line that is defined in the first dielectric layer; an upper wafer including a second substrate, an isolation layer that is defined in an upper surface of the second substrate, a second dielectric layer, bonded to an upper surface of the first dielectric layer, that covers a lower surface of the second substrate and that includes at least one portion defined in the lower surface of the second substrate below and in contact with the isolation layer, and a third dielectric layer that is defined on the upper surface of the second substrate, and a second wiring line that is defined on the third dielectric layer; and a through via passing through, under the second wiring line, the third dielectric layer, the isolation layer, the second dielectric layer under the isolation layer and the first dielectric layer, and coupling the second wiring line and the first wiring line.

## Claims

### Claim 1

A semiconductor device comprising:
a lower wafer including a first substrate, a first dielectric layer that is defined on the first substrate, and a first wiring line that is defined in the first dielectric layer;
an upper wafer including a second substrate, an isolation layer that is defined in an upper surface of the second substrate, a second dielectric layer, bonded to an upper surface of the first dielectric layer, that covers a lower surface of the second substrate and that includes at least one portion defined in the lower surface of the second substrate below and in contact with the isolation layer, and a third dielectric layer that is defined on the upper surface of the second substrate, and a second wiring line that is defined on the third dielectric layer; and
a through via passing through, under the second wiring line, the third dielectric layer, the isolation layer, the second dielectric layer under the isolation layer and the first dielectric layer, and coupling the second wiring line and the first wiring line.

### Claim 2 (depends on 1)

The semiconductor device according to claim 1, further comprising:
a dummy isolation layer defined in the upper surface of the second substrate and disposed around the isolation layer,
wherein the isolation layer and the at least one portion of the second dielectric layer in contact with the isolation layer together extend from the upper surface to the lower surface through the second substrate.

### Claim 3 (depends on 1)

The semiconductor device according to claim 1, wherein the at least one portion of the second dielectric layer extends upward from the lower surface of the second substrate to a lower surface of the isolation layer.

### Claim 4 (depends on 1)

The semiconductor device according to claim 1, wherein a width of a lower surface of the isolation layer is larger than a width of a top surface of the at least one portion of the second dielectric layer.

### Claim 5 (depends on 4)

The semiconductor device according to claim 4, wherein an inner sidewall of the second substrate, defined by the isolation layer and the at least one portion of the second dielectric layer, has a step shape.

### Claim 6 (depends on 4)

The semiconductor device according to claim 4, wherein the at least one portion of the second dielectric layer has a constant width from the lower surface of the second substrate to the lower surface of the isolation layer.

### Claim 7 (depends on 1)

The semiconductor device according to claim 1, wherein the isolation layer has a width that narrows from an upper surface to the lower surface of the isolation layer.

### Claim 8 (depends on 7)

The semiconductor device according to claim 7, wherein the at least one portion of the second dielectric layer has a width that widens from the lower surface of the isolation layer to the lower surface of the second substrate.

### Claim 9 (depends on 7)

The semiconductor device according to claim 7, wherein the at least one portion of the second dielectric layer has a width that narrows from the lower surface of the isolation layer to the lower surface of the second substrate.

### Claim 10 (depends on 1)

The semiconductor device according to claim 1, wherein the second dielectric layer includes at least two portions defined and spaced apart in the lower surface of the second substrate, below and in contact with the isolation layer.

### Claim 11 (depends on 10)

The semiconductor device according to claim 10, further comprising:
a dummy isolation layer defined in the upper surface of the second substrate and disposed around the isolation layer.

### Claim 12 (depends on 10)

The semiconductor device according to claim 10, further comprising:
a dummy isolation layer defined in the upper surface of the second substrate and disposed along opposite sides of the isolation layer.

### Claim 13 (depends on 11)

The semiconductor device according to claim 11, wherein the through via comprises:
a first via passing through the isolation layer, the second dielectric layer under the isolation layer, and the first dielectric layer; and
a second via passing through the third dielectric layer under the second wiring line, and coupled to the first via.

### Claim 14 (depends on 1)

The semiconductor device according to claim 1, wherein the lower wafer includes a memory cell array that is defined on the first substrate, and the upper wafer includes a logic circuit that is defined on the second substrate and controls the memory cell array.

### Claim 15 (depends on 14)

The semiconductor device according to claim 14,
wherein the first wiring line is electrically coupled to the memory cell array,
wherein the second wiring line is electrically coupled to the logic circuit, and
wherein the memory cell array is electrically coupled to the logic circuit through the first wiring line, the second wiring line and the through via.

### Claim 16

A semiconductor device comprising:
a lower wafer including a first substrate, a first dielectric layer that is defined on the first substrate, and a first wiring line that is defined in the first dielectric layer;
an upper wafer including a second substrate, an isolation layer that is defined in an upper surface of the second substrate, a through hole that extends from a lower surface of the second substrate towards the upper surface to expose a lower surface of the isolation layer, a second dielectric layer that fills the through hole, covers the lower surface of the second substrate and is bonded to an upper surface of the first dielectric layer, a third dielectric layer that is defined on the upper surface of the second substrate, and a second wiring line that is defined on the third dielectric layer; and
a through via passing through, under the second wiring line, the third dielectric layer, the isolation layer, the second dielectric layer under the isolation layer and the first dielectric layer, and coupling the second wiring line and the first wiring line.

### Claim 17

A method for manufacturing a semiconductor device, comprising:
forming isolation layers in a front surface of an upper wafer substrate;
forming a through hole that exposes one of the isolation layers, through the upper wafer substrate from a back surface of the upper wafer substrate facing away from the front surface;
forming a first dielectric layer that fills the through hole and covers the back surface;
defining a lower wafer including a lower wafer substrate, a second dielectric layer defined on the lower wafer substrate, and a first wiring line disposed in the second dielectric layer;
bonding a top surface of the second dielectric layer of the lower wafer and a bottom surface of the first dielectric layer;
forming a third dielectric layer on the front surface of the upper wafer substrate;
forming a through via that passes through the third dielectric layer, the one isolation layer, the first dielectric layer under the one isolation layer and the second dielectric layer, and couples to the first wiring line; and
forming, on the third dielectric layer, a second wiring line that is coupled to the through via.

### Claim 18 (depends on 17)

The method according to claim 17, further comprising:
planarizing, before the bonding of the top surface of the second dielectric layer and the bottom surface of the first dielectric layer, the bottom surface of the first dielectric layer and the top surface of the second dielectric layer through a CMP process; and
performing a plasma treatment or a wet pretreatment on the bottom surface of the first dielectric layer and the top surface of the second dielectric layer, which are planarized.

### Claim 19 (depends on 17)

The method according to claim 17, further comprising:
forming, after the bonding of the top surface of the second dielectric layer and the bottom surface of the first dielectric layer and before the forming of the third dielectric layer, a circuit element on the front surface of the upper wafer substrate.

### Claim 20 (depends on 19)

The method according to claim 19,
wherein the lower wafer includes a memory cell array that is coupled to the first wiring line, and
wherein the circuit element includes a logic circuit that is coupled to the second wiring line and controls the memory cell array.