# US 2022/0045006 A1 · Semiconductor device with porous insulating layers and method for fabricating the same

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- Number: US 2022/0045006 A1
- Document ID: US20220045006A1
- Status: Published application
- Kind: A1
- Application number: 16/984,828
- Filed: 2020-08-04
- Published: 2022-02-10
- Earliest claimed: 2020-08-04
- Assignees: Nanya Technology Corporation
- Applicants: Nanya Technology Corporation
- Inventors: TSE-YAO HUANG
- Web page: https://patentgrep.com/patent/US20220045006A1

## CPC

- H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
- H10P 14/665: {Porous materials}
- H10W 20/033: {in openings in dielectrics}
- H10W 20/063: {by forming conductive members before forming protective insulating material}
- H10W 20/0633: {using subtractive patterning of the conductive members}
- H10W 20/0698: {Local interconnections}
- H10W 20/072: {of dielectric parts comprising air gaps}
- H10W 20/076: {in via holes or trenches}
- H10W 20/083: {the openings being via holes penetrating underlying conductors}
- H10W 20/42: Vias, e.g. via plugs
- H10W 20/4462: {Carbon or carbon-containing materials, e.g. graphene}
- H10W 20/46: comprising air gaps
- H10W 20/47: comprising two or more dielectric layers having different properties, e.g. different dielectric constants
- H10W 20/48: Insulating materials thereof
- H10W 20/495: {Capacitive arrangements or effects of, or between wiring layers}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes.

## Claims

### Claim 1

A semiconductor device, comprising:
a substrate;
a top contact positioned above the substrate;
a top conductive layer positioned on the top contact;
porous insulating layers positioned on two sides of the top contact;
first framework layers positioned on bottom surfaces of the porous insulating layers and sidewalls of the porous insulating layers; and
a second framework layer positioned between the top contact and the porous insulating layers, positioned on bottom surface of the top contact, and positioned on top surface of the porous insulating layers.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, further comprising covering layers positioned between the top contact and the second framework layer positioned between the top contact and the porous insulating layers.

### Claim 3 (depends on 2)

The semiconductor device of claim 2, wherein the first framework layers and the second framework layer are formed of a material comprising carbons having hexagonal crystal structures.

### Claim 4 (depends on 2)

The semiconductor device of claim 2, wherein the first framework layers and the second framework layer are formed graphene, graphite, or the like.

### Claim 5 (depends on 3)

The semiconductor device of claim 3, wherein thicknesses of the covering layers are gradually decreased toward the substrate.

### Claim 6 (depends on 5)

The semiconductor device of claim 5, wherein bottommost points of the covering layers are contacting the second framework layer positioned on the bottom surface of the top contact.

### Claim 7 (depends on 6)

The semiconductor device of claim 6, wherein the covering layers are formed of aluminum carbide, aluminum nitride, tungsten carbide, or tungsten nitride.

### Claim 8 (depends on 3)

The semiconductor device of claim 3, wherein porosities of the porous insulating layers are between about 30% and about 95%.

### Claim 9 (depends on 8)

The semiconductor device of claim 8, further comprising a bottom conductive layer below the top contact and a bottom contact positioned below the bottom conductive layer, wherein a width of the top contact is equal to or less than a width of the bottom contact.

### Claim 10 (depends on 9)

The semiconductor device of claim 9, further comprising spacers positioned on sidewalls of the top conductive layer.

### Claim 11

A semiconductor device, comprising:
a substrate;
a top contact positioned above the substrate;
a top conductive layer positioned on the top contact;
porous insulating layers positioned on two sides of the top contact;
a first framework layer positioned on bottom surfaces of the porous insulating layers, sidewalls of the porous insulating layers, and on bottom surface of the top contact; and
a second framework layer positioned between the top contact and the porous insulating layers, between the top contact and the first framework layers, and positioned on top surface of the porous insulating layers.

### Claim 12 (depends on 11)

The semiconductor device of claim 11, further comprising covering layers positioned between the top contact and the second framework layer positioned between the top contact and the porous insulating layers.

### Claim 13

A method for fabricating a semiconductor device, comprising:
providing a substrate;
forming an insulating layer above the substrate;
forming a first opening in the insulating layer;
conformally forming a first framework layer in the first opening;
forming an energy-removable layer on the first framework layer and filling the first opening;
forming a second opening along the energy-removable layer and the first framework layer;
conformally forming a second framework layer in the second opening;
forming a top contact on the second framework layer and filling the second opening and forming a top conductive layer on the top contact; and
performing an energy treatment to transform the energy-removable layer into porous insulating layers on two sides of the top contact.

### Claim 14 (depends on 13)

The method for fabricating the semiconductor device of claim 13, further comprising a step of forming covering layers on sidewalls of the second framework layer and in the second opening.

### Claim 15 (depends on 14)

The method for fabricating the semiconductor device of claim 14, wherein the covering layers are formed of aluminum carbide, aluminum nitride, tungsten carbide, or tungsten nitride.

### Claim 16 (depends on 15)

The method for fabricating the semiconductor device of claim 15, wherein the first framework layer and the second framework layer are formed of a material comprising carbons having hexagonal crystal structures.

### Claim 17 (depends on 16)

The method for fabricating the semiconductor device of claim 16, wherein porosities of the porous insulating layers are between about 30% and about 95%.

### Claim 18 (depends on 17)

The method for fabricating the semiconductor device of claim 17, wherein the energy-removable layer comprises a base material and a decomposable porogen material.

### Claim 19 (depends on 18)

The method for fabricating the semiconductor device of claim 18, wherein the base material comprises methylsilsesquioxane, low-dielectric materials, or silicon oxide.

### Claim 20 (depends on 19)

The method for fabricating the semiconductor device of claim 19, wherein an energy source of the energy treatment is heat, light, or a combination thereof.