# US 2022/0045005 A1 · Three-dimensional memory device including bump-containing bit lines and methods for manufacturing the same

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- Number: US 2022/0045005 A1
- Document ID: US20220045005A1
- Status: Published application
- Kind: A1
- Application number: 16/984,700
- Filed: 2020-08-04
- Published: 2022-02-10
- Earliest claimed: 2020-08-04
- Assignees: SanDisk Technologies LLC
- Applicants: Sandisk Technologies LLC
- Inventors: Zhixin CUI; Yukihiro SAKOTSUBO
- Web page: https://patentgrep.com/patent/US20220045005A1

## CPC

- H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
- H10B 41/27: the channels comprising vertical portions, e.g. U-shaped channels
- H10B 43/27: the channels comprising vertical portions, e.g. U-shaped channels
- H10B 43/40: characterised by the peripheral circuit region
- H10B 43/50: characterised by the boundary region between the core and peripheral circuit regions
- H10W 20/056: {by filling conductive material into holes, grooves or trenches}
- H10W 20/0693: {by forming self-aligned vias}
- H10W 20/0698: {Local interconnections}
- H10W 20/083: {the openings being via holes penetrating underlying conductors}
- H10W 20/42: Vias, e.g. via plugs
- H10W 20/435: {Cross-sectional shapes or dispositions of interconnections}
- H10W 90/00: Package configurations
- H10W 20/069: {by forming self-aligned vias or self-aligned contact plugs}
- H10W 72/01935: {by plating, e.g. electroless plating or electroplating}
- H10W 72/01938: {in gaseous form, e.g. by CVD or PVD}
- H10W 72/01953: {by etching}
- H10W 72/932: {Plan-view shape, i.e. in top view}
- H10W 72/941: {Dispositions of bond pads}
- H10W 72/9445: {Top-view layouts, e.g. mirror arrays}
- H10W 72/951: {Materials of bond pads}
- H10W 80/312: {characterised by the direct bonding of electrically conductive pads}
- H10W 80/327: {characterised by the direct bonding of insulating parts, e.g. of silicon oxide layers}
- H10W 80/701: {characterised by the pads after the direct bonding}
- H10W 90/24: at least one of the stacked chips being laterally offset from a neighbouring stacked chip, e.g. chip stacks having a staircase shape
- H10W 90/28: the stacked chips having different sizes, e.g. chip stacks having a pyramidal shape
- H10W 90/297: {characterised by the through-semiconductor vias [TSVs] in the stacked chips}
- H10W 90/722: {between stacked chips}
- H10W 90/792: {between multiple chips}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10B: ELECTRONIC MEMORY DEVICES

## Abstract

A semiconductor die can include an alternating stack of insulating layers and electrically conductive layers located on a substrate, memory stack structures extending through the alternating stack, drain regions located at a first end of a respective one of the vertical semiconductor channels of a memory stack structure, and bit lines extending over the drain regions and electrically connected to a respective subset of the drain regions. At least of a subset of the bit lines includes bump-containing bit lines. Each of the bump-containing bit lines includes a line portion and a bump portion that protrudes upward from a top surface of the line portion by a bump height. Bit line contact via structures overlie the bit lines and contact a bump portion of a respective one of the bump-containing bit lines.

## Claims

### Claim 1

A semiconductor structure comprising a first semiconductor die, wherein the first semiconductor die comprises:
an alternating stack of insulating layers and electrically conductive layers located on a first substrate;
memory stack structures extending through the alternating stack, wherein each of the memory stack structures comprises a respective vertical semiconductor channel and a respective memory film;
drain regions located at a first end of a respective one of the vertical semiconductor channels;
bit lines extending over the drain regions and electrically connected to a respective subset of the drain regions by at least one conductive via structure, wherein at least a subset of the bit lines comprises bump-containing bit lines, and each of the bump-containing bit lines comprises a line portion and a bump portion that protrudes upward from a top surface of the line portion by a bump height; and
bit line contact via structures overlying the bit lines and contacting a bump portion of a respective one of the bump-containing bit lines.

### Claim 2 (depends on 1)

The semiconductor structure of claim 1, wherein:
the bit lines have a periodic pitch along a first horizontal direction and laterally extend along a second horizontal direction that is perpendicular to the first horizontal direction;
the top surface of the line portion comprises a planar top surface;
the line portion has a uniform height between a planar bottom surface and the planar top surface, and the bump portion protrudes upward from the planar top surface of the line portion by a bump height;
each of the bump portions comprises a pair of lengthwise sidewall segments that are parallel to the second horizontal direction and have a same width as a width of the line portion of each of the bump-containing bit lines.

### Claim 3 (depends on 2)

The semiconductor structure of claim 2, wherein each of the bump portions comprises a pair of widthwise sidewall segments that are not parallel to the second horizontal direction and adjoined to vertical edges of the pair of lengthwise sidewall segments and adjoined to horizontal edges of a planar top surface of a line portion of a respective one of the bump-containing bit lines.

### Claim 4 (depends on 3)

The semiconductor structure of claim 3, wherein the pair of widthwise sidewall segments is parallel to the first horizontal direction and has a same width along the first horizontal direction as each of the line portions of the bump-containing bit lines.

### Claim 5 (depends on 3)

The semiconductor structure of claim 3, wherein the pair of widthwise sidewall segments is at a tile angle with respect to the second horizontal direction, the tilt angle being greater than 0 degree and less than 45 degrees.

### Claim 6 (depends on 5)

The semiconductor structure of claim 5, wherein widthwise sidewall segments of multiple bump portions of the bump-containing bit lines are located within a same Euclidean vertical plane that is at the angle with respect to a vertical plane that is perpendicular to the first horizontal direction.

### Claim 7 (depends on 2)

The semiconductor structure of claim 2, wherein the bit line contact via structures contact a top surface and upper portions of lengthwise sidewall segments of the respective one of the bump-containing bit lines, and do not contact any line portion of the bump-containing bit lines.

### Claim 8 (depends on 7)

The semiconductor structure of claim 7, wherein:
a horizontal cross-sectional shape of the bump portion of the respective one of the bump-containing bit lines has a length-to-width ratio that is greater than 3, the length-to-width ratio being a ratio of a lateral extent of the bump portion of the respective one of the bump-containing bit lines along the second horizontal direction to a lateral extent of the bump portion of the respective one of the bump-containing bit lines along the first horizontal direction; and
the bit line contact via structures do not contact widthwise sidewall segments of the bump portions that are not parallel to the second horizontal direction.

### Claim 9 (depends on 2)

The semiconductor structure of claim 2, wherein each of the bit line contact via structures is laterally elongated along the second horizontal direction, has a width along the first horizontal direction that is not greater than the periodic pitch of the bit lines, and has a length along the second horizontal direction that is at least twice the width.

### Claim 10 (depends on 1)

The semiconductor structure of claim 1, wherein the first semiconductor die comprises first bonding pads embedded in a first pad-level dielectric layer and contacting a top surface of a respective one of the bit line contact via structures.

### Claim 11 (depends on 10)

The semiconductor structure of claim 10, wherein the bump portions of the bump-containing bit lines are arranged such that:
each pair of bump portions is laterally spaced apart along the first horizontal direction at least by a maximum lateral dimension of each bonding pad along the first horizontal direction; and
each pair of bump portions is laterally spaced apart along the second horizontal direction at least by a maximum lateral dimension of each bonding pad along the second horizontal direction.

### Claim 12 (depends on 10)

The semiconductor structure of claim 10, further comprising a second semiconductor die comprising second bonding pads, wherein the first bonding pads are bonded to the second bonding pads.

### Claim 13 (depends on 12)

The semiconductor structure of claim 12, wherein the second semiconductor die further comprises:
peripheral circuit semiconductor devices are located on a second substrate;
dielectric material layers embedding metal interconnect structures and electrically connected to the semiconductor devices; and
second bonding pads embedded in a second pad-level dielectric layer that is located in the dielectric material layers, wherein the second bonding pads are bonded to a respective one of the first bonding pads.

### Claim 14

A method of forming a semiconductor structure that comprises a first semiconductor die, the method comprising:
forming a three-dimensional memory array including memory stack structures vertically extending through an alternating stack of insulating layers and electrically conductive layers over a first substrate, wherein each of the memory stack structures comprises a respective vertical semiconductor channel and a respective memory film, and a drain region is disposed on a top end of each of the vertical semiconductor channels;
forming conductive via structures embedded within at least one connection-level dielectric layer over the drain regions;
forming bit lines on physically exposed top surfaces of the conductive via structures,
masking a first area of each of the bit lines with a respective patterned mask material portion without covering a second area of each of the bit lines;
vertically recessing portions of the bit lines that are not masked by the patterned mask material portions by performing an anisotropic etch process, wherein the bit lines are converted into bump-containing bit lines, and each of the bump-containing bit lines comprises a line portion having a uniform height between a planar bottom surface and a planar top surface and a bump portion that protrudes upward from a horizontal plane including the planar top surface of the line portion by a bump height; and
forming bit line contact via structures on a bump portion of a respective one of the bump-containing bit lines.

### Claim 15 (depends on 14)

The method of claim 14, wherein:
the bit lines have a periodic pitch along a first horizontal direction, and laterally extend along a second horizontal direction that is perpendicular to the first horizontal direction;
the patterned mask material portions comprise patterned portions of a photoresist layer that is applied over the bit lines and is patterned by lithographic exposure and development; and
each patterned portion of the photoresist layer has a width along the first horizontal direction that is not greater than the periodic pitch along the first horizontal direction.

### Claim 16 (depends on 15)

The method of claim 15, wherein:
the patterned mask material portions comprise patterned portions of a photoresist layer that is applied over the bit lines and is patterned by lithographic exposure and development; and
each patterned portion of the photoresist layer laterally extends along a horizontal direction that is at a tilt angle with respect to the second horizontal direction over a respective plurality of bit lines, wherein the tilt angle is greater than 0 degrees and is less than 45 degrees.

### Claim 17 (depends on 14)

The method of claim 14, further comprising:
forming a bit-line-level dielectric layer over the at least one connection-level dielectric layer;
forming line trenches laterally extending along the second horizontal direction through the bit-line-level dielectric layer, wherein top surfaces of a respective subset of the conductive via structures are physically exposed underneath each of the line trenches;
forming the bit lines by depositing at least one conductive material in the line trenches,
wherein:
each patterned mask material portion covers a respective portion of the bit-line-level dielectric layer;
portions of the bit-line-level dielectric layer that are covered by the patterned mask material portions have a respective top surface that is coplanar with top surfaces of the bump portions of the bit lines; and
portions of the bit-line-level dielectric layer that are not covered by the patterned mask material portions are vertically recessed from a horizontal plane including the top surfaces of the bump portions of the bit lines.

### Claim 18 (depends on 14)

The method of claim 14, further comprising:
forming a via-level dielectric layer over the bump-containing bit lines;
forming via cavities extending through the via-level dielectric layer, wherein a top surface and upper portions of a pair of lengthwise sidewall segments of a respective bump portion are physically exposed underneath each of the via cavities; and
forming the bit line contact via structures on a respective one of the bump portions by depositing at least one conductive material in the via cavities.

### Claim 19 (depends on 14)

The method of claim 14, further comprising:
forming a first pad-level dielectric layer over the bit line contact via structures; and
forming first bonding pads in the first pad-level dielectric layer directly on a top surface of a respective one of the bit line contact via structures.

### Claim 20 (depends on 19)

The method of claim 19, further comprising:
providing a second semiconductor die that comprises:
semiconductor devices located on a second substrate,
dielectric material layers embedding metal interconnect structures and electrically connected to the semiconductor devices, and
second bonding pads embedded in a second pad-level dielectric layer that is located in the dielectric material layers; and
bonding the second bonding pads to a respective one of the first bonding pads to form a bonded assembly including the first semiconductor die and the second semiconductor die.