# US 2022/0045003 A1 · Integrated circuit devices including metal wires and methods of forming the same

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- Number: US 2022/0045003 A1
- Document ID: US20220045003A1
- Status: Published application
- Kind: A1
- Application number: 17/066,526
- Filed: 2020-10-09
- Published: 2022-02-10
- Earliest claimed: 2020-08-07
- Assignees: Samsung Electronics Co., Ltd.
- Applicants: Samsung Electronics Co., Ltd.
- Inventors: TAEYONG BAE; HOONSEOK SEO
- Web page: https://patentgrep.com/patent/US20220045003A1

## CPC

- H10W 20/435: {Cross-sectional shapes or dispositions of interconnections}
- H10W 20/035: {combinations of barrier, adhesion or liner layers, e.g. multi-layered barrier layers}
- H10W 20/056: {by filling conductive material into holes, grooves or trenches}
- H10W 20/063: {by forming conductive members before forming protective insulating material}
- H10W 20/0633: {using subtractive patterning of the conductive members}
- H10W 20/069: {by forming self-aligned vias or self-aligned contact plugs}
- H10W 20/0693: {by forming self-aligned vias}
- H10W 20/074: {of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers}
- H10W 20/084: {for dual-damascene structures}
- H10W 20/089: {using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning}
- H10W 20/42: Vias, e.g. via plugs
- H10W 20/425: {Barrier, adhesion or liner layers}
- H10W 20/432: {comprising crossing interconnections}
- H10W 20/438: {Interconnections with multiple fill metals, e.g. having different metals in wide and narrow interconnections, or having different metals in vias and in trenches}
- H10W 20/4403: {based on metals, e.g. alloys, metal silicides (H10W20/4484 takes precedence)}
- H10W 20/4421: {the principal metal being copper}
- H10W 20/4437: {the principal metal being a transition metal}
- H10W 20/47: comprising two or more dielectric layers having different properties, e.g. different dielectric constants
- H10W 20/076: {in via holes or trenches}
- H10W 20/077: {on sidewalls or on top surfaces of conductors (H10W20/076 takes precedence)}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

Integrated circuit devices and methods of forming the same are provided. The integrated circuit devices may include a first insulating layer and a plurality of metal wires on the first insulating layer. The plurality of metal wires may include a first metal wire including a first upper surface and a first lower surface that faces the first insulating layer and a second metal wire including a second upper surface and a second lower surface that faces the first insulating layer and is coplanar with the first lower surface. The first metal wire may have a first width monotonically decreasing from the first lower surface to the first upper surface, and the second metal wire may have a second width monotonically increasing from the second lower surface to the second upper surface.

## Claims

### Claim 1

An integrated circuit device comprising:
a first insulating layer; and
a plurality of metal wires on the first insulating layer,
wherein the plurality of metal wires comprises:
a first metal wire comprising a first upper surface and a first lower surface that faces the first insulating layer, the first metal wire having a first width monotonically decreasing from the first lower surface to the first upper surface; and
a second metal wire comprising a second upper surface and a second lower surface that faces the first insulating layer and is coplanar with the first lower surface, the second metal wire having a second width monotonically increasing from the second lower surface to the second upper surface.

### Claim 2 (depends on 1)

The integrated circuit device of claim 1, wherein the first width of the first lower surface of the first metal wire is less than the second width of the second upper surface of the second metal wire.

### Claim 3 (depends on 1)

The integrated circuit device of claim 1, wherein the first metal wire comprises a plurality of first metal wires that are spaced apart from each other in a first direction, and the second metal wire comprises two second metal wires that are spaced apart from each other in the first direction, and
the plurality of first metal wires are between the two second metal wires.

### Claim 4 (depends on 1)

The integrated circuit device of claim 1, wherein the second metal wire comprises a first metal element, and the first metal wire is devoid of the first metal element.

### Claim 5 (depends on 4)

The integrated circuit device of claim 4, wherein both the first metal wire and the second metal wire comprise a second metal element.

### Claim 6 (depends on 5)

The integrated circuit device of claim 5, wherein the second metal element is ruthenium (Ru), molybdenum (Mo), cobalt (Co), or tungsten (W).

### Claim 7 (depends on 5)

The integrated circuit device of claim 5, wherein the second metal wire comprises a first metal layer comprising the first metal element, and a second metal layer comprising the second metal element, and
the second metal layer extends from a lower surface of the first metal layer onto a sidewall of the first metal layer.

### Claim 8 (depends on 4)

The integrated circuit device of claim 4, wherein the first metal element is copper (Cu).

### Claim 9 (depends on 1)

The integrated circuit device of claim 1, further comprising:
a second insulating layer on the first insulating layer; and
a lower etch stop layer extending between the first insulating layer and the second insulating layer and extending on a sidewall of the first metal wire.

### Claim 10 (depends on 9)

The integrated circuit device of claim 9, wherein the second metal wire extends through the lower etch stop layer.

### Claim 11 (depends on 1)

The integrated circuit device of claim 1, further comprising:
an upper etch stop layer on the first metal wire,
wherein the upper etch stop layer comprises a lower surface contacting the first upper surface of the first metal wire, and the second upper surface of the second metal wire is not higher than the lower surface of the upper etch stop layer.

### Claim 12

An integrated circuit device comprising:
a first insulating layer and a second insulating layer that are sequentially stacked;
a lower etch stop layer extending between the first insulating layer and the second insulating layer; and
a plurality of metal wires on the first insulating layer and in the second insulating layer, the plurality of metal wires comprising a first metal wire and a second metal wire,
wherein the lower etch stop layer extends on a sidewall of the first metal wire from a lower surface to an upper surface of the first metal wire, and the second metal wire extends through the lower etch stop layer.

### Claim 13 (depends on 12)

The integrated circuit device of claim 12, further comprising:
an upper etch stop layer on the first metal wire,
wherein the upper etch stop layer comprises a lower surface contacting the upper surface of the first metal wire, and an upper surface of the second metal wire is not higher than the lower surface of the upper etch stop layer.

### Claim 14 (depends on 13)

The integrated circuit device of claim 13, wherein the lower surface of the first metal wire is coplanar with a lower surface of the second metal wire.

### Claim 15 (depends on 12)

The integrated circuit device of claim 12, wherein the second metal wire comprises a first metal element, and the first metal wire is devoid of the first metal element.

### Claim 16 (depends on 15)

The integrated circuit device of claim 15, wherein both the first metal wire and the second metal wire comprise a second metal element.

### Claim 17

A method of forming an integrated circuit device, the method comprising:
forming a first metal wire on a first insulating layer, the first metal wire comprising a first lower surface that faces the first insulating layer;
forming a second insulating layer on the first metal wire and the first insulating layer;
forming an opening extending through the second insulating layer; and
forming a second metal wire in the opening, the second metal wire comprising a second lower surface that faces the first insulating layer and is coplanar with the first lower surface.

### Claim 18 (depends on 17)

The method of claim 17, wherein forming the first metal wire comprises:
forming a first metal layer on the first insulating layer; and
etching the first metal layer to form the first metal wire.

### Claim 19 (depends on 17)

The method of claim 17, wherein forming the second metal wire comprises:
forming a second metal layer on an upper surface of the second insulating layer and in the opening; and
removing the second metal layer until the upper surface of the second insulating layer is exposed.

### Claim 20 (depends on 19)

The method of claim 19, wherein the second metal layer comprises a first metal element, and the first metal wire is devoid of the first metal element.