# US 2022/0044992 A1 · Semiconductor package

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- Number: US 2022/0044992 A1
- Document ID: US20220044992A1
- Status: Published application
- Kind: A1
- Application number: 17/509,046
- Filed: 2021-10-24
- Published: 2022-02-10
- Earliest claimed: 2018-12-18
- Assignees: Samsung Electronics Co., Ltd.
- Applicants: Samsung Electronics Co., Ltd.
- Inventors: Jung Ho PARK; Jong Youn KIM; Min Jun BAE
- Web page: https://patentgrep.com/patent/US20220044992A1

## CPC

- H10W 70/65: Shapes or dispositions of interconnections
- H10P 72/74: {using temporarily an auxiliary support}
- H10W 40/22: characterised by their shape, e.g. having conical or cylindrical projections
- H10W 70/611: {for connecting multiple chips together}
- H10W 70/685: comprising multiple insulating layers
- H10W 74/117: {the substrate having spherical bumps for external connection}
- H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts}
- H10P 72/7424: {used as a support during the manufacture of self-supporting substrates}
- H10P 72/743: {used as a support during manufacture of interconnect decals or build up layers}
- H10W 40/70: Fillings or auxiliary members in containers or in encapsulations for thermal protection or control
- H10W 70/05: of insulating or insulated package substrates, or of interposers, or of redistribution layers (manufacture or treatment of leadframes H10W70/04)
- H10W 70/099: {Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers}
- H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40)
- H10W 70/69: Insulating materials thereof
- H10W 72/072: {of bump connectors}
- H10W 72/07207: {Temporary substrates, e.g. removable substrates}
- H10W 72/073: {of die-attach connectors}
- H10W 72/07307: {the auxiliary member being a temporary substrate, e.g. a removable substrate}
- H10W 72/07352: {changes in structures or sizes}
- H10W 72/07354: {changes in dispositions}
- H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu}
- H10W 72/29: Bond pads specially adapted therefor
- H10W 72/321: {Structures or relative sizes of die-attach connectors}
- H10W 72/325: {Die-attach connectors having a filler embedded in a matrix}
- H10W 72/347: {Dispositions of multiple die-attach connectors}
- H10W 72/351: {Materials of die-attach connectors}
- H10W 72/354: {comprising polymers}
- H10W 72/877: {Bump connectors and die-attach connectors}
- H10W 74/019: {using temporary auxiliary substrates (H10W74/017 takes precedence)}
- H10W 74/142: {the encapsulations exposing the passive side of the semiconductor body}
- H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/736: {between a chip and a stacked lead frame, conducting package substrate or heat sink}
- H10W 90/794: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor package includes a redistribution substrate having first and second surfaces opposed to each other, and including an insulation member, a plurality of redistribution layers on different levels in the insulation member, and a redistribution via having a shape narrowing from the second surface toward the first surface in a first direction; a plurality of UBM layers, each including a UBM pad on the first surface of the redistribution substrate, and a UBM via having a shape narrowing in a second direction, opposite to the first direction; and at least one semiconductor chip on the second surface of the redistribution substrate, and having a plurality of contact pads electrically connected to the redistribution layer adjacent to the second surface among the plurality of redistribution layers.

## Claims

### Claim at position 1

-23. (canceled)

### Claim 24

A method of manufacturing a semiconductor package, the method comprising:
forming a first redistribution layer on a first carrier;
forming a redistribution structure on the first carrier to cover the first redistribution layer, wherein the redistribution structure includes a plurality of insulation layers and a plurality of second redistribution layers respectively disposed between the plurality of insulation layers, each of the plurality of second redistribution layers having a connection via connected to an adjacent one of the first redistribution layer and the plurality of second redistribution layers;
forming a plurality of bonding pads on the redistribution structure, each of the plurality of bonding pads having a bonding via connected to an uppermost redistribution layer among the plurality of second redistribution layers;
mounting at least one semiconductor chip having a plurality of contact pads on the redistribution structure such that the plurality of contact pads are connected to the plurality of bonding pads, respectively;
attaching a second carrier to an upper surface of the at least one semiconductor chip;
removing the first carrier from a surface of the redistribution structure, in which the first redistribution layer is disposed;
forming a base insulation layer on the surface of the redistribution structure to cover the first redistribution layer; and
forming an underbump metallurgy (UBM) pad on the base insulation layer, the UBM pad having a UBM via connected to the first redistribution layer.

### Claim 25 (depends on 24)

The method of claim 24, wherein the UBM pad has a thickness greater than that of each of the plurality of second redistribution layers.

### Claim 26 (depends on 25)

The method of claim 25, wherein the UBM pad has a thickness of 10 μm or more

### Claim 27 (depends on 24)

The method of claim 24,
wherein each of the connection via and the bonding via has a tapered structure narrowed toward a first direction, and
wherein the UBM via has a tapered structure narrowed toward a second direction opposed to the first direction.

### Claim 28 (depends on 24)

The method of claim 24, further comprising:
after the forming the bonding pad, disposing at least one semiconductor chip on the base insulation layer to electrically connected to the bonding pad.

### Claim 29 (depends on 24)

The method of claim 24, further comprising:
between the mounting the at least one semiconductor chip and the attaching the second carrier, forming a molding portion encapsulating the at least one semiconductor chip and grinding the molding portion to expose the upper surface of the at least one semiconductor chip.

### Claim 30 (depends on 24)

The method of claim 24, wherein the mounting the at least one semiconductor chip comprises connecting the contact pads of the at least one semiconductor chip to the bonding pads, respectively, by using connection bumps

### Claim 31 (depends on 30)

The method of claim 30, wherein the mounting the at least one semiconductor chip comprises forming an underfill resin to surround the connection bumps between the at least one semiconductor chip and the redistribution structure.

### Claim 32 (depends on 24)

The method of claim 24, wherein each of the plurality of insulation layers comprises a photosensitive insulating material.

### Claim 33 (depends on 32)

The method of claim 32, wherein the base insulation layers comprise a photosensitive insulating material.

### Claim 34 (depends on 32)

The method of claim 32, wherein the base insulation layers comprise an insulating material different from that of each of the plurality of insulation layers.

### Claim 35 (depends on 24)

The method of claim 24, wherein the UBM via has a width greater than that of the connection via.

### Claim 36 (depends on 24)

The method of claim 24, wherein each of the plurality of redistribution layers is formed along with the connection via by a same process.

### Claim 37 (depends on 24)

The method of claim 24, wherein the UBM pad is formed along with the UBM via by a same process.

### Claim 38

A method of manufacturing a semiconductor package, the method comprising:
forming a planar conductive pattern on a first carrier;
forming a redistribution structure on the first carrier, wherein the redistribution structure includes a plurality of insulation layers, and a plurality of redistribution layers between the plurality of first insulation layers, each of the plurality of redistribution layers having a connection via connected to an adjacent one of planar conductive pattern and the plurality of redistribution layers;
forming a plurality of bonding pads on the redistribution structure, each of the plurality of bonding pads having a bonding via connected to an uppermost redistribution layer among the plurality of redistribution layers
disposing at least one semiconductor chip to electrically connect the plurality of bonding pads;
forming a molding portion encapsulating the at least one semiconductor chip;
grinding the molding portion to expose the upper surface of the at least one semiconductor chip;
attaching a second carrier to the upper surface of the at least one semiconductor;
removing the first carrier from a surface of the redistribution structure, in which the planar conductive pattern is disposed;
forming a base insulation layer on the surface of the redistribution structure to cover the planar conductive pattern; and
forming an underbump metallurgy (UBM) pad on the base insulation layer, the UBM pad having a UBM via connected to the planar conductive pattern.

### Claim 39 (depends on 38)

The method of claim 38,
wherein the UBM pad has a thickness greater than that of each of the plurality of redistribution layers,
wherein the connection via has a tapered structure narrowed toward a first direction, and
wherein the UBM via has a tapered structure narrowed toward a second direction opposite to the first direction.

### Claim 40 (depends on 38)

The method of claim 38, wherein each of the plurality of insulation layers comprises a photosensitive insulating material and the base insulation layers comprise a photosensitive insulating material.

### Claim 41

A method of manufacturing a semiconductor package, the method comprising:
forming a planar conductive pattern on a first carrier;
forming a redistribution structure on the first carrier, the redistribution structure including a plurality of insulation layers and a plurality of redistribution layers between the plurality of first insulation layers;
forming a plurality of bonding pads on the redistribution structure, each of the plurality of bonding pads having a bonding via connected to an uppermost redistribution layer among the plurality of redistribution layers;
disposing at least one semiconductor chip to electrically connect the plurality of bonding pads;
attaching a second carrier to an upper surface of the at least one semiconductor chip;
removing the first carrier from a surface of the redistribution structure in which the planar conductive pattern is disposed;
forming a base insulation layer on the surface of the redistribution structure to cover the planar conductive pattern; and
forming an underbump metallurgy (UBM) pad on the base insulation layer, the UBM pad having a UBM via connected to the planar conductive pattern.

### Claim 42 (depends on 41)

The method of claim 41, wherein the forming the redistribution structure comprises:
forming a first insulation layer on the first carrier to cover the planar conductive pattern;
forming a first hole in the first insulation layer, the first hole exposing a portion of the planar conductive pattern;
forming a first redistribution layer on the first insulation layer, the first redistribution layer having a first connection via in the first hole connected to the exposed portion of the planar conductive pattern;
forming a second insulation layer on the first insulation layer to cover the first redistribution layer;
forming a second hole in the second insulation layer, the second hole exposing a portion of the first redistribution layer;
forming a second redistribution layer on the second insulation layer, the second redistribution layer having a second connection via in the second hole connected to the exposed portion of the first redistribution layer; and
forming a third insulation layer on the second insulation layer to cover the second redistribution layer.

### Claim 43 (depends on 42)

The method of claim 42,
wherein the UBM pad has a thickness greater than that of each of the plurality of redistribution layers,
wherein each of the first and the second connection vias has a tapered structure narrowed toward a first direction, and
wherein the UBM via has a tapered structure narrowed toward a second direction opposed to the first direction.