# US 2022/0044973 A1 · Vertical stacked nanosheet cmos transistors with different work function metals

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- Number: US 2022/0044973 A1
- Document ID: US20220044973A1
- Status: Published application
- Kind: A1
- Application number: 17/497,173
- Filed: 2021-10-08
- Published: 2022-02-10
- Earliest claimed: 2019-03-15
- Assignees: International Business Machines Corporation
- Applicants: International Business Machines Corporation
- Inventors: Kangguo CHENG; Juntao LI; Ruilong Xie; Chanro PARK
- Web page: https://patentgrep.com/patent/US20220044973A1

## CPC

- H10D 84/038: {using silicon technology, e.g. SiGe}
- B82Y 10/00: Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
- H10D 30/019: {of FETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 30/031: {of thin-film transistors [TFT]}
- H10D 30/501: {FETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 30/6713: {characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes}
- H10D 30/6735: {having gates fully surrounding the channels, e.g. gate-all-around}
- H10D 30/6739: {Conductor-insulator-semiconductor electrodes}
- H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)}
- H10D 62/121: {oriented parallel to substrates}
- H10D 64/01: Manufacture or treatment
- H10D 64/01318: {the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN (comprising a layer of alloys of Si, Ge or C H10D64/01314)}
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 64/667: {the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN workfunction layers (having lateral variation H10D64/671)}
- H10D 84/0167: {Manufacturing their channels}
- H10D 84/017: {Manufacturing their source or drain regions, e.g. silicided source or drain regions}
- H10D 84/0177: {the gate conductors having different materials or different implants}
- H10D 84/85: Complementary IGFETs, e.g. CMOS
- H10D 84/851: {comprising IGFETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 88/00: Three-dimensional [3D] integrated devices
- H10D 88/01: {Manufacture or treatment}
- H10P 14/3411: {Silicon, silicon germanium or germanium}
- H10P 14/3462: {Nanowires}
- H10D 64/018: {Spacers formed inside holes at the prospective gate locations, e.g. holes left by removing dummy gates}
- H10D 84/0179: {the gate conductors having different shapes or dimensions}
- H10D 84/83135: {the IGFETs characterised by having different gate conductor materials or different gate conductor implants}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A method for forming a semiconductor device includes forming a structure having at least a first nanosheet stack for a first device, a second nanosheet stack for a second device and disposed over the first nanosheet stack, a disposable gate structure, and a gate spacer. The disposable gate structure and sacrificial layers of the first and second nanosheet stacks are removed thereby forming a plurality of cavities. A conformal gate dielectric layer is formed in the plurality cavities and surrounding at least portions of the first and second nanosheet stacks. A first conformal work function layer is formed in contact with the gate dielectric layer. Portions of the first conformal work function layer are removed without using a mask from at least the second nanosheet stack. A second conformal work function layer is formed on exposed portions of the gate dielectric layer.

## Claims

### Claim 1

A semiconductor device comprising at least:
a first nanosheet stack for a first device;
a second nanosheet stack for a second device, wherein the second nanosheet stack is disposed on top of the first nanosheet stack; and
a gate structure wrapping around the first nanosheet stack and the second nanosheet stack, wherein the gate structure comprises
a gate dielectric layer surrounding a first set of nanosheet layers of the first nanosheet stack and a second set of nanosheet layers of the second nanosheet stack;
a first work function layer in contact with at least a first portion of the gate dielectric layer surrounding the first set of nanosheet layers and pinched off between each nanosheet layer of the first set of nanosheet layers;
a second work function layer in contact with at least second portion of the gate dielectric layer surrounding the second set of nanosheet layers, wherein a gap exists between portions of the second work function layer between each nanosheet layer of the second set of nanosheet layers; and
a gate conductor layer formed in contact with the second work function layer, wherein the gate conductor layer fills the gap between the portions of the second work function layer.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, further comprising:
a first source layer and a first drain layer of the first doping type formed in contact with the first nanosheet stack;
a dielectric layer formed top of and in contact with at least the first source layer and the first drain layer; and
a second source layer and a second drain layer of the second doping type formed in contact with the second nanosheet stack and further formed in contact with a top surface of the dielectric layer.

### Claim 3 (depends on 1)

The semiconductor device of claim 1, wherein the first work function layer comprises a different material than the second work function layer.

### Claim 4

A semiconductor device comprising at least:
a first nanosheet stack for a first device;
a second nanosheet stack for a second device, wherein the second nanosheet stack is disposed on top of the first nanosheet stack; and
a gate structure wrapping around the first nanosheet stack and the second nanosheet stack, wherein the gate structure comprises
a gate dielectric layer;
a first work function layer in contact with at least a first portion of the gate dielectric layer;
a second work function layer in contact with at least second portion of the gate dielectric layer surrounding nanosheet layers of the second nanosheet stack; and
a gate conductor layer formed in contact with the second work function layer.

### Claim 5 (depends on 4)

The semiconductor device of claim 4, wherein the gate dielectric layer surrounds a first set of nanosheet layers of the first nanosheet stack and a second set of nanosheet layers of the second nanosheet stack.

### Claim 6 (depends on 4)

The semiconductor device of claim 4, wherein the first work function layer is pinched off between each nanosheet layer of the first set of nanosheet layers.

### Claim 7 (depends on 4)

The semiconductor device of claim 4, wherein the gate conductor layer fills a gap between portions of the second work function layer between nanosheet layers of the second nanosheet stack.

### Claim 8

A method for forming a semiconductor device, the method comprising at least:
forming a structure comprising at least a first nanosheet stack including a first set of alternating nanosheet and sacrificial layers for a first device, a second nanosheet stack disposed over the first nanosheet stack and including a second set of alternating nanosheet and sacrificial layers for a second device, a disposable gate structure formed in contact with the second nanosheet stack, and a gate spacer wrapping the disposable gate structure;
removing the disposable gate structure and sacrificial layers of the first and second nanosheet stacks thereby forming a plurality of cavities;
forming a conformal gate dielectric layer in the plurality cavities and surrounding at least portions of each nanosheet layer of the first and second nanosheet stacks;
forming a first conformal work function layer in contact with the gate dielectric layer;
removing, without using a mask, portions of the first conformal work function layer from at least the second nanosheet stack and sidewalls of the first nanosheet stack;
forming a second conformal work function layer on exposed portions of the gate dielectric layer; and
forming a gate conductive layer in contact with the second conformal work function layer.

### Claim 9 (depends on 8)

The method of claim 8, wherein forming the structure comprises:
epitaxially growing a first insulating layer in contact with a substrate;
epitaxially growing the first set of alternating nanosheet and sacrificial layers of the first nanosheet stack on the first insulating layer;
epitaxially growing a second insulating layer in on top of and in contact with the first nanosheet stack; and
epitaxially growing the second set of alternating nanosheet and sacrificial layers of the second nanosheet stack on top of and in contact with the second insulating layer.

### Claim 10 (depends on 9)

The method of claim 9, wherein the first and second insulating layers are epitaxially grown with a first germanium concentration and the sacrificial layers of the first and second nanosheet stacks are epitaxially grown with a second germanium concentration.

### Claim 11 (depends on 9)

The method of claim 9, wherein the sacrificial layers of the first nanosheet stack are epitaxially grown with a thickness that is less than a thickness of the sacrificial layers of the second nanosheet stack.

### Claim 12 (depends on 9)

The method of claim 9, wherein forming the structure further comprises:
forming a hardmask layer on top of and in contact with the second nanosheet stack.

### Claim 13 (depends on 9)

The method of claim 9, wherein forming the structure further comprises:
patterning the first insulating layer, the second insulating layer, the first nanosheet stack, and the second nanosheet stack into a plurality of vertical stack structures.

### Claim 14 (depends on 9)

The method of claim 9, wherein forming the structure further comprises:
replacing the first and second insulating layers with first and second isolation layers, respectively;
removing portions of the second isolation layer and portions of the sacrificial layers of the first and second nanosheet stacks not underlying the disposable gate structure;
laterally recessing end portions of the sacrificial layers; and
forming inner spacers in contact with the recessed end portions of the sacrificial layers.

### Claim 15 (depends on 14)

The method of claim 14, further comprising:
forming a first source and a first drain in contact with at least the inner spacers and nanosheet layers of the first nanosheet stack;
forming a dielectric layer on the first source and a first drain; and
forming a second source and a second drain in contact with at least the inner spacers and the nanosheet layers of the first nanosheet stack.

### Claim 16 (depends on 15)

The method of claim 15, further comprising:
forming an inter-layer dielectric on and in contact with a top surface of the second source and a second drain, and sidewalls of the gate spacer.

### Claim 17 (depends on 8)

The method of claim 8, wherein the disposable gate structure is formed by:
forming a dielectric layer over and in contact with portions of the first and second nanosheet stacks corresponding to a channel region; and
forming a gate cap layer over and in contact with the dielectric layer.

### Claim 18 (depends on 8)

The method of claim 8, wherein forming the conformal gate dielectric layer further comprises:
forming the conformal gate dielectric layer in contact with at least the inner sidewalls of the gate spacer.

### Claim 19 (depends on 8)

The method of claim 8, wherein forming the first conformal work function layer comprises:
depositing a conformal layer of an n-type work function material.

### Claim 20 (depends on 8)

The method of claim 8, wherein forming the first conformal work function layer comprises:
pinching off the first conformal work function layer between the nanosheet layers of the first nanosheet stack, where a cavity remains between each nanosheet layer of the second nanosheet stack.