# US 2022/0044964 A1 · Semiconductor structure and method for manufacturing same

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- Number: US 2022/0044964 A1
- Document ID: US20220044964A1
- Status: Published application
- Kind: A1
- Application number: 17/509,162
- Filed: 2021-10-25
- Published: 2022-02-10
- Earliest claimed: 2020-07-16
- Assignees: Changxin Memory Technologies, Inc.
- Applicants: Changxin Memory Technologies, Inc.
- Inventors: Jingwen LU
- Web page: https://patentgrep.com/patent/US20220044964A1

## CPC

- H10W 20/063: {by forming conductive members before forming protective insulating material}
- H10W 20/077: {on sidewalls or on top surfaces of conductors (H10W20/076 takes precedence)}
- H10B 12/31: {having a storage electrode stacked over the transistor}
- H10B 12/482: {Bit lines}
- H10B 12/485: {Bit line contacts}
- H10P 50/71: {using masks for conductive or resistive materials}
- H10W 20/032: {of conductive barrier, adhesion or liner layers}
- H10W 20/0633: {using subtractive patterning of the conductive members}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10B: ELECTRONIC MEMORY DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

Provided are a semiconductor structure and a method for manufacturing the same. The method for manufacturing a semiconductor structure includes that a substrate is provided, and a first structure is formed on the substrate; a first supporting layer is formed, the first supporting layer covering the first structure; a second supporting layer is formed, the second supporting layer covering the first supporting layer; and the first supporting layer and the second supporting layer on an upper surface of the first structure, and the first supporting layer between the first structure and the second supporting layer are removed, a top surface of the second supporting layer being higher than the top surface of the first structure.

## Claims

### Claim 1

A method for manufacturing a semiconductor structure, comprising:
providing a substrate, a first structure forming on the substrate;
forming a first supporting layer, the first supporting layer covering the first structure;
forming a second supporting layer, the second supporting layer covering the first supporting layer; and
removing the first supporting layer on an upper surface of the first structure and between the first structure and the second supporting layer as well as the second supporting layer on an upper surface of the first structure, a top surface of the second supporting layer being higher than a top surface of the first structure.

### Claim 2 (depends on 1)

The method of claim 1, wherein forming a first structure on the substrate comprises:
forming a double-bit-line to-be-etched structure on the upper surface of the substrate; and
forming first sidewall structures on sidewalls of the double-bit-line to-be-etched structure, the double-bit-line to-be-etched structure and the first sidewall structures together forming the first structure.

### Claim 3 (depends on 2)

The method of claim 2, wherein forming a double-bit-line to-be-etched structure on the upper surface of the substrate comprises:
forming a bit line material layer including a bit line barrier layer, a bit line conductive layer and a covering insulating layer on the upper surface of the substrate; and
etching the bit line material layer to obtain the double-bit-line to-be-etched structure, the substrate being exposed between adjacent double-bit-line to-be-etched structures.

### Claim 4 (depends on 2)

The method of claim 2, further comprising: after removing the first supporting layer between the first structure and the second supporting layer,
forming a bit line mask layer on a surface of the double-bit-line to-be-etched structure and surfaces of bit line supporting structures, an opening being provided in the bit line mask layer, the opening defining two adjacent bit lines, and the first supporting layer and the second supporting layer together constituting the bit line supporting structures;
etching the double-bit-line to-be-etched structure based on the bit line mask layer to obtain the two adjacent bit lines;
forming second sidewall structures on exposed sidewalls of the two adjacent bit lines; and
removing the bit line mask layer and the bit line supporting structures to expose the first sidewall structures.

### Claim 5 (depends on 4)

The method of claim 4, wherein a center line of the opening of the bit line mask layer coincides with a center line of the second supporting layer on both sides of the first structure.

### Claim 6 (depends on 4)

The method of claim 4, wherein forming the bit line mask layer on the surface of the double-bit-line to-be-etched structure and the surface of the bit line supporting structures comprises:
forming a bit line mask material layer on the surface of the double-bit-line to-be-etched structure and a surface of the second supporting layer, a partial region of the bit line mask material layer being recessed to form a step; and
etching the bit line mask material layer based on the step of the bit line mask material layer to obtain the bit line mask layer.

### Claim 7 (depends on 6)

The method of claim 6, wherein a thickness of the bit lines is positively related to a thickness of the bit line mask material layer.

### Claim 8 (depends on 4)

The method of claim 4, wherein forming the bit line mask layer on the surface of the double-bit-line to-be-etched structure and the surfaces of the bit line supporting structures comprises:
forming a bit line mask material layer on the surfaces of the bit line supporting structures; and
patterning the bit line mask material layer to obtain the bit line mask layer.

### Claim 9 (depends on 4)

The method of claim 4, wherein both a material of the first supporting layer and a material of the bit line mask layer comprise silicon oxide, and the second supporting layer comprises a polysilicon layer.

### Claim 10 (depends on 9)

The method of claim 9, wherein a first sidewall structure comprises a first silicon nitride layer, a silicon oxide layer and a second silicon nitride layer which are sequentially stacked from the sidewall of the double-bit-line to-be-etched structure to outside, the second silicon nitride layer also covering an upper surface of the double-bit-line to-be-etched structure and an exposed upper surface of the substrate.

### Claim 11 (depends on 1)

A semiconductor structure, manufactured by the method of claim 1.