# US 2022/0044962 A1 · Semiconductor device, manufacturing method thereof, solid-state imaging device, and electronic apparatus

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- Number: US 2022/0044962 A1
- Document ID: US20220044962A1
- Status: Published application
- Kind: A1
- Application number: 17/508,476
- Filed: 2021-10-22
- Published: 2022-02-10
- Earliest claimed: 2011-04-19
- Assignees: Sony Group Corporation
- Applicants: Sony Group Corporation
- Inventors: Masaki Okamoto
- Web page: https://patentgrep.com/patent/US20220044962A1

## CPC

- H10W 20/082: {the openings being tapered via holes}
- H04N 25/78: Readout circuits for addressed sensors, e.g. output amplifiers or A/D converters
- H10F 39/014: {of CMOS image sensors}
- H10F 39/018: {of hybrid image sensors}
- H10F 39/026: {Wafer-level processing}
- H10F 39/18: Complementary metal-oxide-semiconductor [CMOS] image sensors; Photodiode array image sensors
- H10F 39/199: {Back-illuminated image sensors}
- H10F 39/8063: {Microlenses}
- H10F 39/809: {of hybrid image sensors}
- H10F 39/811: {Interconnections}
- H10W 20/023: {the interconnections being through-semiconductor vias}
- H10W 20/0234: {comprising etching via holes that stop on pads or on electrodes}
- H10W 20/0242: {comprising etching via holes from the back sides of the chips, wafers or substrates}
- H10W 20/0253: {comprising forming the through-semiconductor vias after stacking of the chips, wafers or substrates}
- H10W 20/0265: {characterised by the sidewall insulation}
- H10W 20/056: {by filling conductive material into holes, grooves or trenches}
- H10W 20/076: {in via holes or trenches}
- H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
- H10W 20/2125: {Top-view shapes}
- H10W 20/2134: {TSVs extending from the semiconductor wafer into back-end-of-line layers}
- H10W 20/216: {characterised by dielectric material at least partially filling the via holes, e.g. covering the through-semiconductor vias in the via holes}
- H10W 20/42: Vias, e.g. via plugs
- H10W 72/013: {of die-attach connectors}
- H10W 70/099: {Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers}
- H10W 72/0198: {batch processes}
- H10W 72/073: {of die-attach connectors}
- H10W 72/354: {comprising polymers}
- H10W 90/22: the stacked chips being on both top and bottom sides of a package substrate, interposer or RDL
- H10W 90/297: {characterised by the through-semiconductor vias [TSVs] in the stacked chips}
- H10W 90/732: {between stacked chips}
- H10W 99/00: Subject matter not provided for in other groups of this subclass
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H04N: PICTORIAL COMMUNICATION, e.g. TELEVISION
- H10F: INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION

## Abstract

A method of manufacturing a semiconductor device includes bonding a first semiconductor wafer including a first substrate and a first insulating layer formed to contact one surface of the first substrate, and a second semiconductor wafer including a second substrate and a second insulating layer, forming a third insulating layer, performing etching so that the second insulating layer remains on a second wiring layer, forming a first connection hole, forming an insulating film on the first connection hole, performing etching of the second insulating layer and the insulating film, forming a second connection hole, and forming a first via formed in inner portions of the connection holes and connected to the second wiring layer, wherein a diameter of the first connection hole formed on the other surface of the first substrate is greater than a diameter of the first connection hole formed on the third insulating layer.

## Claims

### Claim 1

A method of manufacturing a semiconductor device comprising:
laminating a first semiconductor wafer including a first substrate and a first insulating layer which is formed so as to come into contact with one surface of the first substrate, and a second semiconductor wafer including a second substrate and a second insulating layer which is formed so as to come into contact with one surface of the second substrate and bonding the first semiconductor wafer and the second semiconductor wafer to each other;
forming a third insulating layer on the other surface of a side opposite to the one surface of the first substrate;
penetrating the third insulating layer, the first substrate, and the first insulating layer, performing etching so as that the second insulating layer remains on a second wiring layer which is formed in the second insulating layer, and forming a first connection hole;
forming an insulating film on the first connection hole;
performing etching of the second insulating layer on the second wiring layer and the insulating film, forming a second connection hole, and exposing the second wiring layer; and
forming a first via which is formed in inner portions of the first and the second connection holes and is connected to the second wiring layer,
wherein a diameter of the first connection hole which is formed on the other surface of the first substrate is greater than a diameter of the first connection hole which is formed on the third insulating layer.

### Claim 2 (depends on 1)

The method of manufacturing a semiconductor device according to claim 1, further comprising:
performing etching of the third insulating layer, the first substrate, and the first insulating layer so that the first insulating layer remains on a first wiring layer formed in the first insulating layer, and forming a third connection hole;
forming the insulating film on the third connection hole;
performing etching of the first insulating layer on the first wiring layer and the insulating film, forming a fourth connection hole, and exposing the first wiring layer; and
forming a second via which is formed in inner portions of the third and the fourth connection holes and is connected to the first wiring layer,
wherein a diameter of the third connection hole which is formed on the other surface of the first substrate is greater than a diameter of the third connection hole which is formed on the third insulating layer, and
a film thickness of the first insulating layer which remains on the first wiring layer is thinner than a film thickness of the second insulating layer which remains on the second wiring layer.

### Claim 3 (depends on 1)

The method of manufacturing a semiconductor device according to claim 1,
wherein the bonding of the first semiconductor wafer and the second semiconductor wafer includes bonding the first semiconductor wafer and the second semiconductor wafer through the first insulating layer and a connection layer which is connected to the second substrate.

### Claim 4 (depends on 1)

The method of manufacturing a semiconductor device according to claim 1,
wherein the bonding of the first semiconductor wafer and the second semiconductor wafer includes bonding the first semiconductor wafer and the second semiconductor wafer through a connection layer which connects the first insulating layer and the second insulating layer to each other.

### Claim 5

A semiconductor device in which a first semiconductor wafer including a first substrate and a first insulating layer which is formed so as to come into contact with one surface of the first substrate, and a second semiconductor wafer including a second substrate and a second insulating layer which is formed so as to come into contact with one surface of the second substrate are laminated and bonded to each other, comprising:
a third insulating layer which is formed on the other surface of a side opposite to the one surface of the first substrate;
a first insulating film which is formed on a side wall of a portion of the first substrate, the first insulating layer, and the second insulating layer in an inner side of a first connection hole which penetrates the third insulating layer, the first substrate, and the first insulating layer and is formed on a portion of the second insulating layer; and
a first via which is formed in an inner side of the first connection hole on which the first insulating film is formed and in an inner side of a second connection hole which is formed so that a second wiring layer formed on the second insulating layer is exposed, and is connected to the second wiring layer,
wherein a diameter of the first connection hole which is formed on the other surface of the first substrate is greater than a diameter of the first connection hole which is formed on the third insulating layer.

### Claim 6

A solid-state imaging device in which a first semiconductor wafer including a first substrate, a first insulating layer which is formed so as to come into contact with one surface of the first substrate, and a pixel array portion, and a second semiconductor wafer including a second substrate, a second insulating layer which is formed so as to come into contact with one surface of the second substrate, and a wiring layer which is formed on the second insulating layer are laminated and bonded to each other, comprising:
a third insulating layer which is formed on the other surface of a side opposite to the one surface of the first substrate;
a first insulating film which is formed on a side wall of a portion of the first substrate, the first insulating layer, and the second insulating layer in an inner side of a first connection hole which penetrates the third insulating layer, the first substrate, and the first insulating layer and is formed on a portion of the second insulating layer; and
a first via which is formed in an inner side of the first connection hole on which the first insulating film is formed and in an inner side of a second connection hole which is formed so that a second wiring layer formed on the second insulating layer is exposed, and is connected to the second wiring layer,
wherein a diameter of the first connection hole which is formed on the other surface of the first substrate is greater than a diameter of the first connection hole which is formed on the third insulating layer.