# US 2022/0044941 A1 · Methods Of Etching Metals In Semiconductor Devices

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- Number: US 2022/0044941 A1
- Document ID: US20220044941A1
- Status: Published application
- Kind: A1
- Application number: 17/509,293
- Filed: 2021-10-25
- Published: 2022-02-10
- Earliest claimed: 2019-09-25
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Wei-Hao Liao; Hsi-Wen Tien; Chih Wei Lu; Pin-Ren Dai; Chung-Ju Lee
- Web page: https://patentgrep.com/patent/US20220044941A1

## CPC

- H10P 50/71: {using masks for conductive or resistive materials}
- H10W 20/063: {by forming conductive members before forming protective insulating material}
- H10P 50/267: {using plasmas}
- H10P 76/405: {characterised by their composition, e.g. multilayer masks}
- H10P 76/4085: {characterised by the processes involved to create the masks}
- H10W 20/0633: {using subtractive patterning of the conductive members}
- H10W 20/075: {of multilayered thin functional dielectric layers}
- H10W 20/089: {using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning}
- H10W 20/42: Vias, e.g. via plugs
- H10W 20/4403: {based on metals, e.g. alloys, metal silicides (H10W20/4484 takes precedence)}
- H10W 20/037: {the barrier, adhesion or liner layers being on top of a main fill metal}
- H10W 20/0523: {by irradiating with ultraviolet or particle radiation}
- H10W 20/054: {by selectively removing parts thereof (H10W20/034 takes precedence)}
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor structure includes a conductive feature disposed over a semiconductor substrate, a via disposed in a first interlayer dielectric (ILD) layer over the conductive feature, and a metal-containing etch-stop layer (ESL) disposed on the via, where the metal-containing ESL includes a first metal and is resistant to etching by a fluorine-containing etchant. The semiconductor structure further includes a conductive line disposed over the metal-containing ESL, where the conductive line includes a second metal different from the first metal and is etchable by the fluorine-containing etchant, and where the via is configured to interconnect the conductive line to the conductive feature. Furthermore, the semiconductor structure includes a second ILD layer disposed over the first ILD layer.

## Claims

### Claim 1

A semiconductor structure, comprising:
a conductive feature disposed over a semiconductor substrate;
a via disposed in a first interlayer dielectric (ILD) layer over the conductive feature;
a metal-containing etch-stop layer (ESL) disposed on the via, wherein the metal-containing ESL includes a first metal and is resistant to etching by a fluorine-containing etchant;
a conductive line disposed over the metal-containing ESL, wherein the conductive line includes a second metal different from the first metal and is etchable by the fluorine-containing etchant, and wherein the via is configured to interconnect the conductive line to the conductive feature; and
a second ILD layer disposed over the first ILD layer.

### Claim 2 (depends on 1)

The semiconductor structure of claim 1, wherein a thickness of the metal-containing ESL is less than a thickness of the conductive line.

### Claim 3 (depends on 1)

The semiconductor structure of claim 1, wherein the metal-containing ESL is a first metal-containing ESL, wherein the via includes a second metal-containing ESL disposed over a via bulk layer, and wherein a composition of the second metal-containing ESL is different from a composition of the first metal-containing ESL.

### Claim 4 (depends on 3)

The semiconductor structure of claim 3, further comprising a barrier layer disposed over the second metal-containing ESL and portions of the first ILD layer, wherein a composition of the barrier layer is different from the composition of the first and the second metal-containing ESL, respectively.

### Claim 5 (depends on 1)

The semiconductor structure of claim 1, wherein the second ILD layer extends to contact a sidewall of the metal-containing ESL.

### Claim 6 (depends on 1)

The semiconductor structure of claim 1, further comprising an ESL over the conductive line and the second ILD layer.

### Claim 7

A semiconductor structure, comprising:
a first interlayer dielectric (ILD) layer disposed over a semiconductor substrate;
a via disposed in the first ILD layer;
an etch-stop layer (ESL) disposed over the first ILD layer, wherein the ESL is resistant to etching by a fluorine-containing etchant;
a conductive line disposed over the ESL; and
a second ILD layer disposed adjacent to the conductive line, wherein the second ILD layer extends between portions of the ESL to directly contact the first ILD layer.

### Claim 8 (depends on 7)

The semiconductor structure of claim 7, wherein the conductive line is etchable by the fluorine-containing etchant.

### Claim 9 (depends on 8)

The semiconductor structure of claim 8, wherein an etching selectivity between the ESL and the conductive line with respect to the fluorine-containing etchant is at least 10.

### Claim 10 (depends on 7)

The semiconductor structure of claim 7, wherein the ESL is a first ESL, wherein the via includes a second ESL disposed over a via bulk layer, and wherein the second ESL has a composition different from the first ESL.

### Claim 11 (depends on 10)

The semiconductor structure of claim 10, wherein the second ESL includes Co.

### Claim 12 (depends on 7)

The semiconductor structure of claim 7, wherein the ESL includes Cu and the conductive line is free of Cu.

### Claim 13 (depends on 7)

The semiconductor structure of claim 7, wherein a thickness of the ESL is less than a thickness of the conductive line.

### Claim 14

A semiconductor structure, comprising:
a via contact disposed in a first interlayer dielectric (ILD) layer, wherein the via contact includes a first etch-stop layer (ESL) disposed over a via bulk layer;
a second ESL disposed over the via contact, wherein the second ESL includes a first metal, and wherein the first and the second ESLs have different compositions;
a conductive line disposed over the second ESL, wherein the conductive line includes a second metal different from the first metal;
a second ILD layer disposed over the first ILD layer, wherein the second ILD layer directly contact sidewalls of the conductive line and the second ESL; and
a third ESL disposed over the second ILD layer.

### Claim 15 (depends on 14)

The semiconductor structure of claim 14, wherein the second ESL is resistant to etching by a fluorine-containing etchant, and wherein the conductive line is etchable by the fluorine-containing etchant.

### Claim 16 (depends on 15)

The semiconductor structure of claim 15, wherein an etching selectivity between the second ESL and the conductive line with respect to the fluorine-containing etchant is at least 10.

### Claim 17 (depends on 14)

The semiconductor structure of claim 14, wherein the first ESL includes Co.

### Claim 18 (depends on 14)

The semiconductor structure of claim 14, further comprising a barrier layer disposed over the first ESL, wherein the barrier layer and the first ESL have different compositions.

### Claim 19 (depends on 14)

The semiconductor structure of claim 14, wherein a thickness of the second ESL is less than a thickness of the conductive line.

### Claim 20 (depends on 14)

The semiconductor structure of claim 14, wherein the second ILD layer directly contacts the first ILD layer.