# US 2022/0044940 A1 · Semiconductor structure and manufacturing method thereof

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- Number: US 2022/0044940 A1
- Document ID: US20220044940A1
- Status: Published application
- Kind: A1
- Application number: 17/468,804
- Filed: 2021-09-08
- Published: 2022-02-10
- Earliest claimed: 2020-08-05
- Assignees: Changxin Memory Technologies, Inc.
- Applicants: Changxin Memory Technologies, Inc.
- Inventors: CHUNG-YEN CHOU
- Web page: https://patentgrep.com/patent/US20220044940A1

## CPC

- H10P 50/73: {using masks for insulating materials}
- H10B 12/00: Dynamic random access memory [DRAM] devices
- H10B 12/0335: {Making a connection between the transistor and the capacitor, e.g. plug}
- H10B 12/09: {with simultaneous manufacture of the peripheral circuit region and memory cells}
- H10B 12/485: {Bit line contacts}
- H10P 76/2041: {Photolithographic processes}
- H10P 76/405: {characterised by their composition, e.g. multilayer masks}
- H10P 76/4085: {characterised by the processes involved to create the masks}
- H10B 12/482: {Bit lines}
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10B: ELECTRONIC MEMORY DEVICES

## Abstract

A semiconductor structure and a manufacturing method thereof are provided. The manufacturing method includes: forming a stacked structure on the substrate, the stacked structure at least including a first material layer, a second material layer and a third material layer from bottom to top; patterning the stacked structure to obtain a first pattern structure; forming a spacer structure on a side wall of the first pattern structure, a top of the spacer structure being not lower than a top of the first material layer; and removing the third material layer, wherein during removing the third material layer, an etching selectivity of the third material layer to the second material layer is greater than 1.

## Claims

### Claim 1

A method for manufacturing a semiconductor structure, comprising:
providing a substrate;
forming a stacked structure on the substrate, the stacked structure at least comprising a first material layer, a second material layer and a third material layer from bottom to top;
patterning the stacked structure to obtain a first pattern structure;
forming a spacer structure on a side wall of the first pattern structure, a top the spacer structure being not lower than a top of the first material layer; and
removing the third material layer, wherein during removing the third material layer, an etching selectivity of the third material layer to the second material layer is greater than 1.

### Claim 2 (depends on 1)

The method for manufacturing the semiconductor structure of claim 1, wherein a thickness of the second material layer is less than that of the third material layer.

### Claim 3 (depends on 1)

The method for manufacturing the semiconductor structure of claim 1, wherein an etching selectivity of the third material layer to the second material layer and the spacer structure is greater than 5.

### Claim 4 (depends on 1)

The method for manufacturing the semiconductor structure of claim 1, wherein forming the spacer structure comprises:
at least forming an isolation material layer on the side walls and an upper surface of the first pattern structure; and
etching the isolation material layer to remove the isolation material layer on the upper surface of the first pattern structure and retain the isolation material layer on the side wall of the first pattern structure, to form the spacer structure.

### Claim 5 (depends on 4)

The method for manufacturing the semiconductor structure of claim 4, wherein the second material layer and the spacer structure are made of a silicon oxide material, and the third material layer is made of a silicon nitride material.

### Claim 6 (depends on 1)

The method for manufacturing the semiconductor structure of claim 1, wherein a thickness of the second material layer is 3 nm to 30 nm, and a thickness of the third material layer is 5 nm to 100 nm.

### Claim 7 (depends on 1)

The method for manufacturing the semiconductor structure of claim 1, wherein when the first pattern structure is a patterned first stacked structure, the method further comprises:
before the patterned first stacked structure is formed, forming a second stacked structure on the substrate;
wherein the second stacked structure is located between the patterned first stacked structure and the substrate.

### Claim 8 (depends on 7)

The method for manufacturing the semiconductor structure of claim 7, wherein before forming the second stacked structure on the substrate, the method further comprises:
patterning the substrate to form an active area;
forming word line structures in the substrate;
forming a bit line structure on the substrate; and
forming a structural layer to be etched on the substrate.

### Claim 9 (depends on 7)

The method for manufacturing the semiconductor structure of claim 7, wherein the substrate comprises an array region and a peripheral circuit region located at a periphery of the array region, and the method further comprises:
forming a photoresist layer, the photoresist layer covering the peripheral circuit region and exposing the array region; and
patterning the second stacked structure by taking the photoresist layer and the first pattern structure as masks.

### Claim 10 (depends on 7)

The method for manufacturing the semiconductor structure of claim 7, wherein the second stacked structure comprises a fourth material layer and a fifth material layer stacked from bottom to top, wherein the first material layer and the fourth material layer are organic mask material layers, and the second material layer and the fifth material layer are hard mask material layers.

### Claim 11 (depends on 7)

The method for manufacturing the semiconductor structure of claim 7, wherein the patterned first stacked structure is a strip structure extending along a first direction, the second stacked structure is a strip structure extending along a second direction, and a projection of the second stacked structure on the substrate is overlapped with a projection of the patterned first stacked structure on the substrate.

### Claim 12 (depends on 11)

The method for manufacturing the semiconductor structure of claim 11, wherein a node contact hole is defined by the patterned first stacked structure and the second stacked structure.

### Claim 13 (depends on 8)

The method for manufacturing the semiconductor structure of claim 8, wherein the structural layer to be etched is etched by taking the second stacked structure and the patterned first stacked structure as masks to form a node contact hole.

### Claim 14 (depends on 1)

A semiconductor structure formed by the method for manufacturing the semiconductor structure of claim 1, comprising:
a substrate;
a first material layer located on the substrate;
a second material layer located on the first material layer and arranged in a stacked manner with the first material layer; and
a spacer structure arranged on a side wall of the first material layer and the second material layer, a top of the spacer structure being not lower than a top of the first material layer.