# US 2022/0044933 A1 · Semiconductor device with reduced critical dimensions

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- Number: US 2022/0044933 A1
- Document ID: US20220044933A1
- Status: Published application
- Kind: A1
- Application number: 17/510,918
- Filed: 2021-10-26
- Published: 2022-02-10
- Earliest claimed: 2019-06-13
- Assignees: Nanya Technology Corporation
- Applicants: Nanya Technology Corporation
- Inventors: KUO-HUI SU
- Web page: https://patentgrep.com/patent/US20220044933A1

## CPC

- H10P 76/4088: {Processes for improving the resolution of the masks}
- H10P 14/6322: {Formation by thermal treatments (formation by plasma treatment H10P14/6319)}
- H10P 14/6334: {using decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition (deposition by physical ablation of a target H10P14/6329)}
- H10P 30/40: into insulating materials
- H10P 50/695: {characterised by the process involved to create the mask, e.g. lift-off masks or sidewalls or to modify the mask}
- H10P 50/71: {using masks for conductive or resistive materials}
- H10P 76/405: {characterised by their composition, e.g. multilayer masks}
- H10P 76/4083: {characterised by their behaviours during the lithography processes, e.g. soluble masks or redeposited masks}
- H10P 76/4085: {characterised by the processes involved to create the masks}
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor structure includes a base layer with a top surface and a plurality of processed areas. A primary pattern is disposed on the top surface of the base layer, wherein the primary pattern has a pattern top surface, a processed area on the pattern top surface, and a sidewall, and the primary pattern has a first critical dimension, and the processed areas are on the part of the top surface of the base layer exposed by the primary pattern. A secondary pattern is disposed on the sidewall of the primary pattern, wherein the secondary pattern has a second critical dimension, and the second critical dimension is smaller than the first critical dimension.

## Claims

### Claim 1

A semiconductor structure, comprising:
a base layer with a top surface;
a primary pattern with a pattern top surface and a sidewall, disposed on the top surface of the base layer, wherein the primary pattern has a first critical dimension;
a plurality of processed areas on the pattern top surface and on a part of the top surface of the base layer exposed by the primary pattern; and
a secondary pattern disposed on the sidewall of the primary pattern, wherein the secondary pattern has a second critical dimension, and the second critical dimension is smaller than the first critical dimension.

### Claim 2 (depends on 1)

The semiconductor structure of claim 1, wherein the base layer and the primary pattern comprise silicon.

### Claim 3 (depends on 2)

The semiconductor structure of claim 2, wherein the secondary pattern comprises silicon dioxide.

### Claim 4 (depends on 2)

The semiconductor structure of claim 2, wherein the base layer comprises a silicon substrate.

### Claim 5 (depends on 2)

The semiconductor structure of claim 2, wherein the primary pattern comprises polysilicon.

### Claim 6 (depends on 1)

The semiconductor structure of claim 1, wherein the processed areas comprise ion implantation damage.

### Claim 7

A semiconductor structure, comprising:
a base layer with a top surface;
a plurality of processed areas on the top surface, wherein the processed areas have a first critical dimension and each of the processed areas has an edge; and
a secondary pattern disposed along the edges of the processed areas on the top surface of the base layer, wherein the secondary pattern has a second critical dimension and the second critical dimension is smaller than the first critical dimension.

### Claim 8 (depends on 7)

The semiconductor structure of claim 7, wherein the base layer comprises silicon.

### Claim 9 (depends on 8)

The semiconductor structure of claim 8, wherein the base layer comprises a silicon substrate.

### Claim 10 (depends on 8)

The semiconductor structure of claim 8, wherein the secondary pattern comprises silicon dioxide.

### Claim 11 (depends on 7)

The semiconductor structure of claim 7, wherein the processed areas comprise ion implantation damage.