# US 2022/0044757 A1 · Adapting an error recovery process in a memory sub-system > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2022/0044757 A1 - Document ID: US20220044757A1 - Status: Published application - Kind: A1 - Application number: 16/989,374 - Filed: 2020-08-10 - Published: 2022-02-10 - Earliest claimed: 2020-08-10 - Assignees: Micron Technology, Inc. - Applicants: Micron Technology, Inc. - Inventors: Zhongguang XU; Murong LANG; Zhenming ZHOU - Web page: https://patentgrep.com/patent/US20220044757A1 ## CPC - G11C 29/50004: {of threshold voltage} - G11C 16/10: Programming or data input circuits - G11C 16/26: Sensing or reading circuits; Data output circuits - G11C 29/12005: {comprising voltage or current generators} - G11C 29/44: Indication or identification of errors, e.g. for repair - G11C 29/52: Protection of memory contents; Detection of errors in memory contents - G11C 11/5642: {Sensing or reading circuits; Data output circuits} - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract A first sequence of operations corresponding to an error recovery process of a memory sub-system is determined. A value corresponding to an operating characteristic of the memory sub-system is determined. The value is compared to a threshold level corresponding to the first sequence of operations to determine whether a condition is satisfied. In response to satisfying the first condition, a second sequence of operations corresponding to the error recovery process is executed. ## Claims ### Claim 1 A method comprising: determining, by a processing device, a first sequence of operations corresponding to an error recovery process of a memory sub-system; determining a value corresponding to an operating characteristic of the memory sub-system; comparing the value to a threshold level corresponding to the first sequence of operations to determine whether a condition is satisfied; and in response to satisfying the condition, executing a second sequence of operations corresponding to the error recovery process. ### Claim 2 (depends on 1) The method of claim 1, wherein the operating characteristic comprises a read retry rate associated with a read retry threshold voltage level. ### Claim 3 (depends on 2) The method of claim 2, wherein the read retry threshold voltage level is selected from a set of read retry threshold voltage levels comprising a first read retry threshold voltage level, a second read retry threshold voltage level, and a third read retry threshold voltage level. ### Claim 4 (depends on 2) The method of claim 2, wherein the read retry rate is determined based on a first count of read retry operations associated with a second read retry threshold voltage level compared to a sum of counts of read retry operations associated with a plurality of read retry threshold voltage levels. ### Claim 5 (depends on 1) The method of claim 1, wherein the first condition is satisfied upon determining the value is greater than the first threshold level. ### Claim 6 (depends on 1) The method of claim 1, wherein the first sequence of operations comprises one or more read retry operations executed using one of a plurality of different read threshold voltage levels. ### Claim 7 (depends on 1) The method of claim 1, further comprising: determining a further value corresponding to the operating characteristic of the memory sub-system; and in response to determining the further value is greater than a second threshold level, executing a third sequence of operations. ### Claim 8 A non-transitory computer readable medium comprising instructions, which when executed by a processing device, cause the processing device to perform operations comprising: determining a value corresponding to a cycle count of a memory sub-system applying a first sequence of operations of an error recovery process; determining the value is within an identified cycle count range of a set of cycle count value ranges; and executing a second sequence of operations corresponding to the identified cycle count range. ### Claim 9 (depends on 8) The non-transitory computer readable medium of claim 8, the operations further comprising determining an updated value corresponding to the cycle count of the memory sub-system and determining the updated value is within another cycle count range of the set of cycle count value ranges. ### Claim 10 (depends on 9) The non-transitory computer readable medium of claim 9, the operations further comprising: executing a third sequence of operations corresponding to the another cycle count range. ### Claim 11 (depends on 10) The non-transitory computer readable medium of claim 10, wherein the third sequence of operations comprises a greater number of read retry operations than the second sequence of operations, and wherein the second sequence of operations comprises a greater number of read retry operations than the first sequence of operations. ### Claim 12 (depends on 8) The non-transitory computer readable medium of claim 8, the operations further comprising: maintaining a data structure comprising a plurality of error recovery process levels, wherein each error recovery process level comprises a cycle count range and a sequence of operations. ### Claim 13 (depends on 12) The non-transitory computer readable medium of claim 12, the operations further comprising performing a look-up operation of the data structure to identify the second sequence of operations corresponding to the identified cycle count range. ### Claim 14 A system comprising: a memory component; and a processing device, operatively coupled with the memory component, to perform operations comprising: determining a first sequence of operations corresponding to an error recovery process of a memory sub-system; determining a value corresponding to an operating characteristic of the memory sub-system; comparing the value to a threshold level corresponding to the first sequence of operations to determine whether a condition is satisfied; and in response to satisfying the condition, executing a second sequence of operations corresponding to the error recovery process. ### Claim 15 (depends on 14) The system of claim 14, wherein the operating characteristic comprises a read retry rate associated with a read retry threshold voltage level. ### Claim 16 (depends on 15) The system of claim 15, wherein the read retry threshold voltage level is selected from a set of read retry threshold voltage levels comprising a first read retry threshold voltage level, a second read retry threshold voltage level, and a third read retry threshold voltage level. ### Claim 17 (depends on 15) The system of claim 15, wherein the read retry rate is determined based on a first count of read retry operations associated with a second read retry threshold voltage level compared to a sum of counts of read retry operations associated with a plurality of read retry threshold voltage levels. ### Claim 18 (depends on 14) The system of claim 14, wherein the first condition is satisfied upon determining the value is greater than the first threshold level. ### Claim 19 (depends on 14) The system of claim 14, wherein the first sequence of operations comprises one or more read retry operations executed using one of a plurality of different read threshold voltage levels. ### Claim 20 (depends on 14) The system of claim 14, wherein the processing device is further to perform operations comprising: determining a further value corresponding to the operating characteristic of the memory sub-system; and in response to determining the further value is greater than a second threshold level, executing a third sequence of operations.