# US 2022/0044748 A1 · Control system with cascade driving circuits and related driving method > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2022/0044748 A1 - Document ID: US20220044748A1 - Status: Published application - Kind: A1 - Application number: 17/363,020 - Filed: 2021-06-30 - Published: 2022-02-10 - Earliest claimed: 2020-08-06 - Assignees: Novatek Microelectronics Corp. - Applicants: NOVATEK Microelectronics Corp. - Inventors: Che-Wei Yeh; Keko-Chun Liang; Yu-Hsiang Wang; Yong-Ren Fang; Yi-Chuan Liu; Yi-Yang Tsai; Po-Hsiang Fang - Web page: https://patentgrep.com/patent/US20220044748A1 ## CPC - G11C 19/28: using semiconductor elements (G11C19/14, G11C19/36 take precedence) - G09G 3/20: for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix {no fixed position being assigned to or needed to be assigned to the individual characters or partial characters} - G09G 2310/0286: Details of a shift registers arranged for use in a driving circuit - G09G 2310/08: Details of timing specific for flat panels, other than clock recovery - G11C: STATIC STORES (semiconductor memory devices H10B) - G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00) ## Abstract A control system includes a plurality of driving circuits coupled in series, which includes a first driving circuit and a second driving circuit. The first driving circuit includes a first receiver, a first transmitter and a replica receiver. The first transmitter is coupled to the first receiver, and the replica receiver is coupled to an output terminal of the first transmitter. The second driving circuit, coupled to the first driving circuit, includes a second receiver and a second transmitter. The second receiver is coupled to the first transmitter, and the second transmitter is coupled to the second receiver. ## Claims ### Claim 1 A control system, comprising: a plurality of driving circuits coupled in series, comprising: a first driving circuit, comprising: a first receiver; a first transmitter, coupled to the first receiver; and a replica receiver, coupled to an output terminal of the first transmitter; and a second driving circuit, coupled to the first driving circuit, comprising: a second receiver, coupled to the first transmitter; and a second transmitter, coupled to the second receiver. ### Claim 2 (depends on 1) The control system of claim 1, wherein the first driving circuit further comprises an output buffer, which is configured to drive a controller based on a data or clock signal. ### Claim 3 (depends on 2) The control system of claim 2, wherein the data or clock signal is sent to the output buffer through the first receiver, the first transmitter and the replica receiver. ### Claim 4 (depends on 2) The control system of claim 2, wherein the replica receiver is in an output path of the data or clock signal used for driving the controller. ### Claim 5 (depends on 1) The control system of claim 1, wherein the first driving circuit and the second driving circuit are configured to drive a controller using a first driving signal and a second driving signal, respectively, and a timing of the second driving circuit outputting the second driving signal to the controller is synchronized with a timing of the first driving circuit outputting the first driving signal to the controller. ### Claim 6 A control system, comprising: a plurality of driving circuits coupled in series, comprising: a first driving circuit, comprising: a first receiver; a first transmitter, coupled to the first receiver; and a first delay circuit, coupled between the first receiver and the first transmitter; and a second driving circuit, coupled to the first driving circuit, comprising: a second receiver; a second transmitter, coupled to the second receiver; and a second delay circuit, coupled between the second receiver and the second transmitter; wherein the first delay circuit and the second delay circuit are configured to synchronize a first driving signal output by the first driving circuit with a second driving signal output by the second driving circuit. ### Claim 7 (depends on 6) The control system of claim 6, further comprising: a controller, coupled to the first driving circuit and the second driving circuit, configured to receive the first driving signal from the first driving circuit and receive the second driving signal from the second driving circuit. ### Claim 8 (depends on 6) The control system of claim 6, wherein each of the first delay circuit and the second delay circuit comprises: a select circuit, comprising a plurality of input terminals, an output terminal and a select terminal; a plurality of flip-flops, each coupled to one of the plurality of input terminals of the select circuit; and a processing circuit, coupled to the output terminal of the select circuit. ### Claim 9 (depends on 8) The control system of claim 8, wherein each of the plurality of flip-flops are connected in series. ### Claim 10 The control system of claim. 8, wherein the plurality of flip-flops are configured to receive clock signals having different phases. ### Claim 11 (depends on 8) The control system of claim 8, wherein the select circuit is configured to selectively output a flag signal from one of the plurality of flip-flops, to synchronize the first driving signal with the second driving signal. ### Claim 12 (depends on 11) The control system of claim 11, wherein the processing circuit is configured to process a signal received by the corresponding driving circuit among the plurality of driving circuits when receiving the flag signal from the select circuit. ### Claim 13 A method of driving a controller for a control system having a plurality of driving circuits coupled in series, the plurality of driving circuits comprising a first driving circuit and a second driving circuit, the method comprising: receiving, by the first driving circuit, a first signal from a previous stage; transmitting, by the first driving circuit, the first signal to the second driving circuit; delaying the first signal with a first delay circuit to generate a second signal in each of the first driving circuit and the second driving circuit; selecting a clock signal from a plurality of clock signals having different phases in a second delay circuit in each of the first driving circuit and the second driving circuit; and controlling a timing of outputting the second signal to the controller by using the selected clock signal, to synchronize the second signal output by the first driving circuit and the second driving circuit. ### Claim 14 (depends on 13) The method of claim 13, wherein the first delay circuit is a coarse delay circuit for providing coarse delay adjustment on the first signal, and the second delay circuit is a fine delay circuit for providing fine delay adjustment on the second signal. ### Claim 15 (depends on 14) The method of claim 14, wherein in the coarse delay circuit, a delay time is generated by passing the first signal through a replica receiver. ### Claim 16 (depends on 14) The method of claim 14, wherein the coarse delay circuit is configured to synchronize the first signal of the first driving circuit and the second driving circuit by selecting different flag signals corresponding to different clock cycles for the first driving circuit and the second driving circuit. ### Claim 17 (depends on 14) The method of claim 14, wherein the fine delay circuit is configured to synchronize the second signal of the first driving circuit and the second driving circuit by selecting different flag signals corresponding to different clock phases for the first driving circuit and the second driving circuit. ### Claim 18 A driving circuit, comprising: a receiver; a transmitter, coupled to the receiver; and a replica receiver, coupled to an output terminal of the transmitter. ### Claim 19 (depends on 18) The driving circuit of claim 18, wherein the driving circuit further comprises an output buffer, which is configured to drive a controller based on a data or clock signal. ### Claim 20 (depends on 19) The driving circuit of claim 19, wherein the data or clock signal is sent to the output buffer through the receiver, the transmitter and the replica receiver. ### Claim 21 (depends on 19) The driving circuit of claim 19, wherein the replica receiver is in an output path of the data or clock signal used for driving the controller. ### Claim 22 A driving circuit, comprising: a receiver; a transmitter, coupled to the receiver; and a delay circuit, coupled between the receiver and the transmitter, configured to output a driving signal; wherein the delay circuit comprises a select circuit coupled to output terminals of a plurality of flip-flops. ### Claim 23 (depends on 22) The driving circuit of claim 22, wherein each of the plurality of flip-flops are connected in series. ### Claim 24 (depends on 22) The driving circuit of claim 22, wherein the plurality of flip-flops are configured to receive clock signals having different phases. ### Claim 25 (depends on 22) The driving circuit of claim 22, wherein the select circuit is configured to selectively output a flag signal from one of the plurality of flip-flops, to synchronize output timing of the driving signal. ### Claim 26 (depends on 25) The driving circuit of claim 25, further comprising a processing circuit configured to process a signal received by the driving circuit when receiving the flag signal from the select circuit.