# US 2022/0044746 A1 · Methods and apparatus for nand flash memory

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- Number: US 2022/0044746 A1
- Document ID: US20220044746A1
- Status: Published application
- Kind: A1
- Application number: 17/506,628
- Filed: 2021-10-20
- Published: 2022-02-10
- Earliest claimed: 2018-11-18
- Assignees: NEO Semiconductor, Inc.
- Applicants: NEO Semiconductor, Inc.
- Inventors: Fu-Chang Hsu
- Web page: https://patentgrep.com/patent/US20220044746A1

## CPC

- G11C 11/5628: {Programming or writing circuits; Data input circuits}
- G11C 16/3459: {Circuits or methods to verify correct programming of nonvolatile memory cells}
- G11C 11/5642: {Sensing or reading circuits; Data output circuits}
- G11C 16/08: Address circuits; Decoders; Word-line control circuits
- G11C 16/12: Programming voltage switching circuits
- G11C 16/24: Bit-line control circuits
- G11C 16/26: Sensing or reading circuits; Data output circuits
- G11C 16/30: Power supply circuits
- G11C 16/32: Timing circuits
- G11C 16/0483: {comprising cells having several storage transistors connected in series}
- G11C 2211/5641: Multilevel memory having cells with different number of storage levels
- G11C 2211/5642: Multilevel memory with buffers, latches, registers at input or output
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

Methods and apparatus for memory operations disclosed. In an embodiment, a method is provided for programming multiple-level-cells. The method includes programming data to single-level-cells (SLC) on SLC word lines using SLC programming operations, applying ramp data to the SLC word lines to determine selected ramp data that matches the data stored in (SLC) cells, and programming multiple-level cells to have a voltage threshold level that is associated with the ramp data. In an embodiment, an apparatus includes a first plane having a plurality of first cell strings coupled to a first page buffer. Each first cell string comprises a plurality of multiple-level cells. The apparatus also includes a second plane having a plurality of second cell strings coupled to a second page buffer. Each second cell string comprises a plurality of single-level cells. The apparatus is also configured so that the first page buffer is connected to communicate with the second page buffer.

## Claims

### Claim 1

A method for programming multiple-level-cells, the method comprising:
programming data to single-level-cells (SLC) on SLC word lines using SLC programming operations;
applying ramp data to the SLC word lines to determine selected ramp data that matches the data stored in (SLC) cells; and
programming multiple-level cells to have a voltage threshold level that is associated with the ramp data.

### Claim 2 (depends on 1)

The method of claim 1, wherein SLC cells storing the data are connected in series, and wherein the method comprises turning on SLC cells having stored data that matches the ramp data applied to the SLC word lines.

### Claim 3 (depends on 1)

The method of claim 1, wherein SLC cells storing the data are connected in parallel, and wherein the method comprises turning off SLC cells having stored data that matches the ramp data applied to the SLC word lines.

### Claim 4 (depends on 1)

The method of claim 1, further comprising performing program-verification in which voltages applied to the multiple level word lines correspond to the ramp data applied to the SLC word lines.

### Claim 5 (depends on 1)

The method of claim 1, wherein the multiple-level cells and SLC cells are located in first and second planes, respectively, and perform operations independently.

### Claim 6

A method for programming an apparatus comprising multiple memory chips, wherein the memory chips comprise cells that can store multiple-level data, the method comprising:
programming first data into a first memory chip using an SLC programming operation;
reading the first data from the first memory chip using an SLC reading operation;
reprogramming the first data into a selected memory chip using a multiple-level-cell programming operation; and
during the operation of reprogramming, programming second data into a second chip using the SLC programming operation.

### Claim 7 (depends on 6)

The method of claim 6, wherein the selected multiple-level cells are located in the first chip.

### Claim 8 (depends on 6)

The method of claim 6, wherein the selected multiple-level cells are located in a third chip.

### Claim 9

An apparatus comprising:
a first plane having a plurality of first cell strings coupled to a first page buffer, wherein each first cell string comprises a plurality of multiple-level cells;
a second plane having a plurality of second cell strings coupled to a second page buffer, wherein each second cell string comprises a plurality of single-level cells; and
wherein the first page buffer is connected to the second page buffer.

### Claim 10 (depends on 9)

The apparatus of claim 9, wherein the plurality of single-level cells are connected to each other in series in a cell string.

### Claim 11 (depends on 9)

The apparatus of claim 9, wherein the plurality of single-level cells are located in multiple cell strings.

### Claim 12 (depends on 9)

The apparatus of claim 9, wherein the plurality of single-level cells store input data and complementary input data for the multiple-level cells.

### Claim 13 (depends on 9)

The apparatus of claim 9, wherein word lines of the plurality of single-level cells receive ramped data to match data stored in the single-level cells during program-verification.