# US 2022/0044734 A1 · Page buffer and semiconductor memory device having the page buffer

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- Number: US 2022/0044734 A1
- Document ID: US20220044734A1
- Status: Published application
- Kind: A1
- Application number: 17/172,730
- Filed: 2021-02-10
- Published: 2022-02-10
- Earliest claimed: 2020-08-06
- Assignees: SK hynix Inc.
- Applicants: SK hynix Inc.
- Inventors: Hyung Jin CHOI
- Web page: https://patentgrep.com/patent/US20220044734A1

## CPC

- G11C 16/24: Bit-line control circuits
- G11C 11/5642: {Sensing or reading circuits; Data output circuits}
- G11C 16/26: Sensing or reading circuits; Data output circuits
- G11C 16/32: Timing circuits
- G11C 16/0483: {comprising cells having several storage transistors connected in series}
- G11C 2211/5642: Multilevel memory with buffers, latches, registers at input or output
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

The present technology relates to a page buffer and a semiconductor memory device including the page buffer. The page buffer includes a sensing node, a bit line controller connected between the sensing node and a bit line. The bit line controller is configured to first precharge and second precharge the sensing node.

## Claims

### Claim 1

A page buffer comprising:
a sensing node;
a bit line controller connected between the sensing node and a bit line, and configured to, during a sensing node precharge operation, perform a first precharge of the sensing node to precharge the sensing node to a first potential level and then perform a second precharge of the sensing node to a second potential level; and
a sub latch for latching sensing data based on a potential level of the sensing node.

### Claim 2 (depends on 1)

The page buffer of claim 1, wherein the bit line controller first precharges the sensing node by forming a first current path and then second precharges the sensing node by forming a second current path during the sensing node precharge operation.

### Claim 3 (depends on 1)

The page buffer of claim 1, wherein the first potential level is lower than the second potential level.

### Claim 4 (depends on 1)

The page buffer of claim 1, wherein the bit line controller comprises:
a first transistor connected between a core voltage and a common sensing node and turned on in response to a first common sensing control signal;
a second transistor connected between the common sensing node and the sensing node and turned on in response to a sensing signal; and
third and fourth transistors connected in series between the core voltage and the sensing node.

### Claim 5 (depends on 4)

The page buffer of claim 4, wherein the third transistor is turned on in response to a potential of a node of the sub latch, and the fourth transistor is turned on in response to a precharge signal.

### Claim 6 (depends on 4)

The page buffer of claim 4, wherein the first and second transistors are NMOS transistors, and the third and fourth transistors are PMOS transistors.

### Claim 7 (depends on 6)

The page buffer of claim 6, wherein the first current path is formed through the first transistor and the second transistor, and
the second current path is formed through the third transistor and the fourth transistor.

### Claim 8 (depends on 1)

The page buffer of claim 1, wherein the first and second precharges are performed simultaneously to increase the potential level of the sensing node to the second potential level.

### Claim 9

A semiconductor memory device comprising:
a memory cell array; and
a plurality of page buffers connected to a plurality of bit lines of the memory cell array, respectively,
wherein each of the plurality of page buffers comprises:
a sensing node;
a bit line controller connected between the sensing node and a bit line, and configured to, during a sensing node precharge operation, perform a first precharge of the sensing node to precharge the sensing node to a first potential level and then perform a second precharge of the sensing node to increase a potential level of the sensing node to a second potential level; and
a sub latch for latching sensing data based on a potential level of the sensing node.

### Claim 10 (depends on 9)

The semiconductor memory device of claim 9, wherein the bit line controller first precharges the sensing node by forming a first current path and then second precharges the sensing node by forming a second current path during the sensing node precharge operation.

### Claim 11 (depends on 9)

The semiconductor memory device of claim 9, wherein the first potential level is lower than the second potential level.

### Claim 12 (depends on 9)

The semiconductor memory device of claim 9, wherein the bit line controller comprises:
a first transistor connected between a core voltage and a common sensing node and turned on in response to a first common sensing control signal;
a second transistor connected between the common sensing node and the sensing node and turned on in response to a sensing signal; and
third and fourth transistors connected in series between the core voltage and the sensing node.

### Claim 13 (depends on 12)

The semiconductor memory device of claim 12, wherein the third transistor is turned on in response to a potential of a node of the sub latch, and the fourth transistor is turned on in response to a precharge signal.

### Claim 14 (depends on 12)

The semiconductor memory device of claim 12, wherein the first and second transistors are NMOS transistors, and the third and fourth transistors are PMOS transistors.

### Claim 15 (depends on 14)

The semiconductor memory device of claim 14, wherein the first current path is formed through the first transistor and the second transistor, and
the second current path is formed through the third transistor and the fourth transistor.

### Claim 16

A page buffer comprising:
a sensing node;
a bit line controller connected between the sensing node and a bit line, and configured to, during a sensing node precharge operation, precharge the sensing node to a first potential level using a first current path, and, after the sensing node has been precharged to the first potential level using the first current path, precharging the sensing node to a second potential level using a second current path; and
a sub latch for latching sensing data based on a potential level of the sensing node.

### Claim 17 (depends on 16)

The page buffer of claim 16, wherein the second potential level is higher than the first potential level.

### Claim 18 (depends on 16)

The page buffer of claim 16, wherein the bit line controller comprises:
a first transistor connected between a core voltage and a common sensing node and turned on in response to a first common sensing control signal;
a second transistor connected between the common sensing node and the sensing node and turned on in response to a sensing signal; and
third and fourth transistors connected in series between the core voltage and the sensing node.

### Claim 19 (depends on 18)

The page buffer of claim 18, wherein the third transistor is turned on in response to a potential of a node of the sub latch, and the fourth transistor is turned on in response to a precharge signal.

### Claim 20 (depends on 18)

The page buffer of claim 18, wherein the first and second transistors are NMOS transistors, and the third and fourth transistors are PMOS transistors.

### Claim 21 (depends on 20)

The page buffer of claim 20, wherein the first current path is formed through the first transistor and the second transistor, and
the second current path is formed through the third transistor and the fourth transistor.