# US 2022/0044733 A1 · Semiconductor memory device and method of operating the same > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2022/0044733 A1 - Document ID: US20220044733A1 - Status: Published application - Kind: A1 - Application number: 17/161,197 - Filed: 2021-01-28 - Published: 2022-02-10 - Earliest claimed: 2020-08-10 - Assignees: SK hynix Inc. - Applicants: SK hynix Inc. - Inventors: Hee Youl LEE - Web page: https://patentgrep.com/patent/US20220044733A1 ## CPC - G11C 11/5635: {Erasing circuits} - G11C 16/16: for erasing blocks, e.g. arrays, words, groups - G11C 16/08: Address circuits; Decoders; Word-line control circuits - G11C 16/24: Bit-line control circuits - G11C 16/30: Power supply circuits - G11C 16/32: Timing circuits - G11C 8/12: Group selection circuits, e.g. for memory block selection, chip selection, array selection - G11C 16/0483: {comprising cells having several storage transistors connected in series} - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract A semiconductor memory device includes a precharge block, a select block, a peripheral circuit, and control logic. The precharge block is connected to bit lines and includes memory cells in an erase state. The select block shares the bit lines with the precharge block and includes memory cells in a program state. The peripheral circuit performs erase operation on the select block. The control logic controls the peripheral circuit to turn on a first circuit connected to the precharge block and apply first voltage to global lines connected to the first circuit when erase voltage is applied to a source line commonly connected to the precharge block and the select block. The memory cells of the precharge block are turned on by the first voltage applied from the global lines, and the erase voltage applied to the source line is transferred to the bit lines through the precharge block. ## Claims ### Claim 1 A semiconductor memory device comprising: a precharge block connected to a plurality of bit lines and including memory cells in an erase state; a select block that shares the plurality of bit lines with the precharge block and includes memory cells in a program state; a peripheral circuit configured to perform an erase operation on the select block; and control logic configured to control the peripheral circuit to turn on a first block select circuit connected to the precharge block and apply a first voltage to global lines connected to the first block select circuit when an erase voltage is applied to a source line commonly connected to the precharge block and the select block, wherein the memory cells of the precharge block are turned on by the first voltage applied from the global lines, and the erase voltage applied to the source line is transferred to the plurality of bit lines through the memory cells of the precharge block. ### Claim 2 (depends on 1) The semiconductor memory device of claim 1, wherein, when the first block select circuit is turned on, the control logic controls the peripheral circuit to turn on a second block select circuit connected to the select block. ### Claim 3 (depends on 1) The semiconductor memory device of claim 1, wherein the global lines include at least one of a global word line and a global select line. ### Claim 4 (depends on 3) The semiconductor memory device of claim 3, wherein, after the erase voltage is transferred to the bit line, the control logic controls the peripheral circuit to turn off the first block select circuit and apply a ground voltage to the global word line. ### Claim 5 (depends on 4) The semiconductor memory device of claim 4, wherein, after the first block select circuit is turned off and the ground voltage starts to be applied to the global word line, the control logic increases a voltage applied to the global select line from a first voltage to a second voltage. ### Claim 6 A semiconductor memory device comprising: a memory cell array including a plurality of memory blocks connected to a plurality of bit lines; a peripheral circuit configured to perform an erase operation on a select block among the plurality of memory blocks; and control logic configured to control the peripheral circuit to turn on a first block select circuit connected to the select block by applying a first voltage to the first block select circuit and apply a second voltage to global lines connected to the first block select circuit when an erase voltage is applied to a source line connected to the select block, wherein memory cells of the select block are turned on by the second voltage applied from the global lines, and the erase voltage applied to the source line is transferred to the plurality of bit lines through the memory cells of the select block. ### Claim 7 (depends on 6) The semiconductor memory device of claim 6, wherein, when the first block select circuit is turned on, the control logic controls the peripheral circuit to turn off a second block select circuit connected to at least one other block that is not an erase target among the plurality of memory blocks. ### Claim 8 (depends on 6) The semiconductor memory device of claim 6, wherein the global lines include at least one of a global word line and a global select line. ### Claim 9 (depends on 8) The semiconductor memory device of claim 8, wherein, after the erase voltage is transferred to the bit line, the control logic controls the peripheral circuit to decrease a voltage applied to the first block select circuit from the first voltage to a third voltage and to apply a ground voltage to the global word line. ### Claim 10 (depends on 9) The semiconductor memory device of claim 9, wherein, after the third voltage is applied to the first block select circuit and the ground voltage is started to be applied to the global word line, the control logic increases a voltage applied to the global select line from the first voltage to a fourth voltage. ### Claim 11 A method of operating a semiconductor memory device including a plurality of memory blocks, the method comprising: turning on a first block select circuit connected to a first memory block among the plurality of memory blocks; turning on memory cells included in the first memory block by applying a first voltage to global lines connected to the first block select circuit; and transferring an erase voltage to a bit line connected to the first memory block by starting an application of the erase voltage to a common source line connected to the first memory block. ### Claim 12 (depends on 11) The method of claim 11, further comprising: applying a ground voltage to a global word line among the global lines after transferring the erase voltage to the bit line connected to the first memory block; and increasing a voltage of a global select line among the global lines from the first voltage to a second voltage. ### Claim 13 (depends on 12) The method of claim 12, wherein the first memory block is a precharge block in an erase state, and the method further comprises turning off the first block select circuit after transferring the erase voltage to the bit line connected to the first memory block. ### Claim 14 (depends on 13) The method of claim 13, further comprising: turning on a second block select circuit connected to a second memory block that is an erase target among the plurality of memory blocks. ### Claim 15 (depends on 12) The method of claim 12, wherein the first memory block is a select block that is an erase target, and the method further comprises decreasing a voltage applied to the first block select circuit from the first voltage to a third voltage after transferring the erase voltage to the bit line connected to the first memory block. ### Claim 16 (depends on 15) The method of claim 15, wherein the first voltage is greater than a largest threshold voltage among threshold voltages of memory cells in the select block. ### Claim 17 A semiconductor memory device comprising: a target block and an erased block respectively including first and second cell strings commonly coupled to a source line and a bit line; first and second circuits configured to respectively couple the target and erased blocks to global lines when turned on; and a control circuit configured to perform an erase operation on the target block by: turning on the second circuit by a second voltage and providing the global lines with a third voltage to turn on the second cell string, during a set period of time, while turning on the first circuit by a first voltage lower than the second voltage, providing the source line with an erase voltage to precharge the bit line through the turned-on second cell string, and providing a fourth voltage to a select line among the global lines after the set period of time. ### Claim 18 A semiconductor memory device comprising: a target block including a cell string coupled to a source line and a bit line; a select circuit configured to couple the target block to global lines when turned on; and a control circuit configured to perform an erase operation on the target block by: applying a first voltage to turn on the select circuit and applying a second voltage to the global lines to turn on the cell string, during a set period of time, the second voltage being lower than the first voltage, applying an erase voltage to the source line to precharge the bit line through the turned-on cell string, applying a third voltage, lower than the first voltage, to turn on the select circuit after the set period of time, and applying a fourth voltage to a select line among the global lines after the set period of time.