# US 2022/0044731 A1 · Acceleration of data queries in memory

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- Number: US 2022/0044731 A1
- Document ID: US20220044731A1
- Status: Published application
- Kind: A1
- Application number: 16/984,452
- Filed: 2020-08-04
- Published: 2022-02-10
- Earliest claimed: 2020-08-04
- Assignees: Micron Technology, Inc.
- Applicants: Micron Technology, Inc.
- Inventors: Mark A. Helm; Joseph T. Pawlowski
- Web page: https://patentgrep.com/patent/US20220044731A1

## CPC

- G11C 5/025: {Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device (geometrical lay-out of the components in integrated circuits, geometrical lay-out of the components in integrated circuits H10D89/10)}
- G11C 16/12: Programming voltage switching circuits
- G06F 11/1048: {using arrangements adapted for a specific error detection or correction feature}
- G11C 7/1084: {Data input buffers, e.g. comprising level conversion circuits, circuits for adapting load}
- G11C 15/046: {using non-volatile storage elements}
- G11C 16/0483: {comprising cells having several storage transistors connected in series}
- G11C 16/24: Bit-line control circuits
- G06F 2201/81: Threshold
- G11C 16/26: Sensing or reading circuits; Data output circuits
- G11C 2029/0411: {Online error correction}
- G11C: STATIC STORES (semiconductor memory devices H10B)
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

The present disclosure includes apparatuses and methods for acceleration of data queries in memory. A number of embodiments include an array of memory cells, and processing circuitry configured to receive, from a host, a query for particular data stored in the array of memory cells, wherein the particular data corresponds to a search key generated by the host, search portions of the array of memory cells for the particular data corresponding to the search key, determine data stored in the portions of the array of memory cells that matches the search key, and transfer the data that matches the search key to the host.

## Claims

### Claim 1

An apparatus, comprising:
an array of memory cells; and
processing circuitry configured to:
receive, from a host, a query for particular data stored in the array of memory cells, wherein the particular data corresponds to a search key generated by the host;
search portions of the array of memory cells for the particular data corresponding to the search key;
determine data stored in the portions of the array of memory cells that corresponds more closely to the search key than other data stored in the portions of the array of memory cells;
perform an error correction operation on the data determined to correspond more closely to the search key;
determine data stored in the portions of the array of memory cells that matches the search key after performing the error correction operation on the data determined to correspond more closely to the search key; and
transfer the data that matches the search key to the host.

### Claim 2 (depends on 1)

The apparatus of claim 1, wherein the processing circuitry is configured to determine the data that matches the search key based on an amount of current conducted by the portions of the array of memory cells.

### Claim 3 (depends on 2)

The apparatus of claim 2, wherein the amount of current conducted by a portion of the array of memory cells is greater when the memory cells in that portion of the array store data corresponding to bits in the search key than when the memory cells in that portion of the array store data that does not correspond to the bits in the search key.

### Claim 4 (depends on 2)

The apparatus of claim 2, wherein the data stored in a portion of the array of memory cells that conducts a greater amount of current than other portions of the array is determined to be the data that matches the search key.

### Claim 5

(canceled)

### Claim 6 (depends on 1)

The apparatus of claim 1, wherein the array and the processing circuitry are formed on a same chip of the apparatus.

### Claim 7 (depends on 1)

The apparatus of claim 1, wherein the circuitry comprises a page buffer.

### Claim 8 (depends on 1)

The apparatus of claim 1, wherein no data stored in the portions of the array of memory cells that does not match the search key is transferred to the host.

### Claim 9

An apparatus, comprising:
an array of memory cells; and
processing circuitry configured to:
receive, from a host, a query for data stored in the array of memory cells, wherein the data corresponds to a search key generated by the host;
search portions of the array of memory cells for the data;
determine data stored in the portions of the array of memory cells that corresponds more closely to the search key than other data stored in the portions of the array of memory cells;
perform an error correction operation on the data determined to correspond more closely to the search key;
determine data stored in the portions of the array of memory cells that matches the query after performing the error correction operation on the data determined to correspond more closely to the search key; and
transfer, to the host, only the data that matches the query.

### Claim 10 (depends on 9)

The apparatus of claim 9, wherein the array of memory cells comprises a database.

### Claim 11 (depends on 9)

The apparatus of claim 9, wherein the array of memory cells is a three-dimensional NAND array of memory cells.

### Claim 12 (depends on 9)

The apparatus of claim 9, wherein the portions of the array of memory cells comprise strings of memory cells.

### Claim 13 (depends on 9)

The apparatus of claim 9, wherein the processing circuitry comprises CMOS under array circuitry.

### Claim 14 (depends on 9)

The apparatus of claim 9, wherein the processing circuitry is configured to determine the data stored in the portions of the array of memory cells that matches the query by:
applying a voltage to each of the portions of the array of memory cells; and
determining the data that matches the query based on an amount of current conducted by each respective portion of the array of memory cells upon the voltage being applied thereto.

### Claim 15 (depends on 9)

The apparatus of claim 9, wherein:
the array of memory cells comprises a plurality of planes of memory cells; and
the processing circuitry comprises a plurality of page buffers;
wherein each respective one of the page buffers corresponds to a different one of the planes of memory cells.

### Claim 16

A method, comprising:
receiving, by a memory device from a host, a query for particular data, wherein the particular data corresponds to a search key generated by the host;
searching, by the memory device, portions of the memory device for the particular data;
counting, by the memory device, a quantity of bits in each of the portions of the memory device that match a corresponding bit in the search key, and correcting, by the memory device, errors in the bits in the portions of the memory device, to determine data stored in the portions of the memory device that matches the query; and
transferring the data that matches the query to the host and refraining from transferring nonmatching data to the host.

### Claim 17 (depends on 16)

The method of claim 16, wherein searching the portions of the memory device for the particular data includes:
sensing, by the memory device, data stored in the portions of the memory device;
performing, by the memory device, an error correction operation on the sensed data; and
decrypting, by the memory device, the sensed data after performing the error correction operation on the sensed data.

### Claim 18 (depends on 16)

The method of claim 16, wherein the method includes encrypting, by the memory device, data stored in the portions of the memory device.

### Claim 19 (depends on 16)

The method of claim 16, wherein the method includes searching each of the portions of the memory device for the particular data in parallel.

### Claim 20

A method, comprising:
generating, by a host, a search key denoting particular data;
setting, by the host, a mismatch bit count for a query for the particular data;
sending, to a memory device by the host, the query for the particular data; and
receiving data that matches the query at the host from the memory device or from a buffer coupled to the host, wherein the data that matches the query is based at least in part on results of a search at the memory device that includes a comparison of the search key and determination of matching data, relative to the search key, stored within the memory device.

### Claim 21

(canceled)

### Claim 22 (depends on 20)

The method of claim 20, wherein the data that matches the query comprises data whose quantity of bits that match a corresponding bit in the search key is greater than the mismatch bit count.

### Claim 23 (depends on 20)

The method of claim 20, wherein the query sent by the host is unencrypted.

### Claim 24 (depends on 20)

The method of claim 20, wherein the data that matches the query received at the host is encrypted.

### Claim 25 (depends on 24)

The method of claim 24, wherein the method includes decrypting, by the host, the encrypted data that matches the query.

### Claim 26

A system, comprising:
a host; and
a memory device coupled to the host;
wherein the host is configured to:
generate a search key to denote particular data; and
send a query for the particular data to the memory device; and
wherein the memory device is configured to, in response to receiving the query:
search portions of the memory device for the particular data;
count a number of bits in each portion of the memory device that match the particular data denoted in the search key, and correct errors in the bits in the portions of the memory device, to determine data stored in the portions of the memory device that matches the query; and
transfer the data that matches the query to the host and refrain from transferring nonmatching data to the host.

### Claim 27 (depends on 26)

The system of claim 26, wherein:
the bits in each portion of the memory device are encrypted; and
the memory device is configured to decrypt the encrypted bits.

### Claim 28

(canceled)

### Claim 29 (depends on 26)

The system of claim 26, wherein the memory device is configured to correct the errors in the bits in the portions of the memory device using an error correction code stored in the memory device.

### Claim 30 (depends on 26)

The system of claim 26, wherein the query comprises a command to search for the particular data.