# US 2022/0044730 A1 · Non-volatile memory device and programming method thereof > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2022/0044730 A1 - Document ID: US20220044730A1 - Status: Published application - Kind: A1 - Application number: 17/510,447 - Filed: 2021-10-26 - Published: 2022-02-10 - Earliest claimed: 2019-04-30 - Assignees: Samsung Electronics Co., Ltd. - Applicants: Samsung Electronics Co., Ltd. - Inventors: Byungsoo Kim; Wandong Kim; Jaeyong Jeong - Web page: https://patentgrep.com/patent/US20220044730A1 ## CPC - G11C 16/10: Programming or data input circuits - G11C 11/5628: {Programming or writing circuits; Data input circuits} - G11C 11/5671: {using charge trapping in an insulator} - G11C 16/0483: {comprising cells having several storage transistors connected in series} - G11C 16/08: Address circuits; Decoders; Word-line control circuits - G11C 16/24: Bit-line control circuits - G11C 16/26: Sensing or reading circuits; Data output circuits - G11C 16/32: Timing circuits - G11C 16/3418: {Disturbance prevention or evaluation; Refreshing of disturbed memory data} - G11C 16/3459: {Circuits or methods to verify correct programming of nonvolatile memory cells} - H10W 80/00: Direct bonding of chips, wafers or substrates - H10W 90/00: Package configurations - G11C 7/04: with means for avoiding disturbances due to temperature effects - G11C 2211/5621: Multilevel programming verification - G11C 2211/5642: Multilevel memory with buffers, latches, registers at input or output - G11C 2216/20: Suspension of programming or erasing cells in an array in order to read other cells in it - H10W 90/792: {between multiple chips} - G11C: STATIC STORES (semiconductor memory devices H10B) - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract A non-volatile memory device includes a memory cell array including memory cells respectively connected to bit lines; and a control logic unit configured to control a program operation with respect to the memory cells. The control logic unit is configured to perform a normal program verify operation with respect to the memory cells by using a normal program verify condition, during the program operation, and, based on a suspend command that is received during the program operation, perform an initial program verify operation with respect to the memory cells by using an initial program verify condition that is different from the normal program verify condition. ## Claims ### Claim 1 A non-volatile memory device comprising: a memory cell array including memory cells respectively connected to bit lines; and a control logic unit configured to control a program operation with respect to the memory cells, wherein the control logic unit is further configured to: perform a normal program verify operation with respect to the memory cells by using a normal program verify condition, during the program operation, and based on a suspend command that is received during the program operation, perform an initial program verify operation with respect to the memory cells by using an initial program verify condition that is different from the normal program verify condition, wherein the normal program verify condition comprises a normal program verify voltage, and the initial program verify condition comprises an initial program verify voltage that is different from the normal program verify voltage. ### Claim 2 (depends on 1) The non-volatile memory device of claim 1, further comprising: a row decoder configured to drive a selected word line connected to the memory cells, wherein the row decoder is further configured to apply the normal program verify voltage to the selected word line during the normal program verify operation and to apply the initial program verify voltage to the selected word line during the initial program verify operation. ### Claim 3 (depends on 2) The non-volatile memory device of claim 2, wherein the initial program verify voltage includes a plurality of initial program verify voltage levels respectively corresponding to a plurality of word line groups, wherein the selected word line corresponds to one of the plurality of word line groups according to a position of the selected word line. ### Claim 4 (depends on 2) The non-volatile memory device of claim 2, wherein the initial program verify voltage includes a first initial program verify voltage level for a first word line and a second initial program verify voltage level for a second word line, wherein the first initial program verify voltage level is different from the second initial program verify voltage level, and wherein the second word line is located above the first word line. ### Claim 5 (depends on 1) The non-volatile memory device of claim 1, wherein the suspend command is received after an N-th program loop of the program operation, wherein N is a natural number that is greater than or equal to 2. ### Claim 6 (depends on 5) The non-volatile memory device of claim 5, wherein the suspend command is a first suspend command, and wherein, based on a second suspend command being received in one of first through (N−1)th program loops of the program operation, the control logic unit is further configured to perform the normal program verify operation with respect to the memory cells by using the normal program verify condition, in response to the second suspend command or a resume command received after the second suspend command. ### Claim 7 (depends on 1) The non-volatile memory device of claim 1, wherein the suspend command is received after programming of the memory cells to an M-th program state has been completed, wherein M is a natural number that is greater than or equal to 2. ### Claim 8 (depends on 7) The non-volatile memory device of claim 7, wherein the suspend command is a first suspend command, and wherein, based on a second suspend command being received before programming of the memory cells to the M-th program state is completed, the control logic unit is configured to perform the normal program verify operation with respect to the memory cells by using the normal program verify condition, in response to the second suspend command or a resume command received after the second suspend command. ### Claim 9 (depends on 1) The non-volatile memory device of claim 1, wherein the suspend command is received after the normal verify operation of an N-th program loop of the program operation, wherein N is a natural number that is greater than or equal to 2. ### Claim 10 (depends on 1) The non-volatile memory device of claim 1, wherein the suspend command is received during a bit line setup section after an N-th program loop of the program operation, wherein N is a natural number that is greater than or equal to 2. ### Claim 11 (depends on 1) The non-volatile memory device of claim 1, wherein the initial program verify operation is performed in response to the suspend command or a resume command that is received after the suspend command. ### Claim 12 (depends on 1) The non-volatile memory device of claim 1, wherein the normal program verify operation is performed in a program loop before the suspend command is received or in a program loop after the initial program verify operation. ### Claim 13 (depends on 1) The non-volatile memory device of claim 1, wherein the normal program verify condition further comprises a normal develop time, and the initial program verify condition further comprises an initial develop time that is different from the normal develop time, and wherein the normal develop time corresponds to a time section between a precharge section of the bit lines and a sensing section of sensing nodes respectively connected to the bit lines, during the normal program verify operation, and the initial develop time corresponds to a time section between the precharge section of the bit lines and the sensing section of the sensing nodes, during the initial program verify operation. ### Claim 14 (depends on 13) The non-volatile memory device of claim 13, further comprising: a page buffer unit including page buffers respectively connected to the bit lines, wherein a first page buffer from among the page buffers comprises: a first transistor connected to a first sensing node that is connected to a first bit line from among the bit lines, and driven by a bit line setup signal; and a second transistor connected between the first bit line and the first sensing node and driven by a bit line connection control signal, and each of the initial develop time and the normal develop time corresponds to a time section from a time point when the bit line setup signal is deactivated to a time point when the bit line connection control signal is deactivated. ### Claim 15 A method of programming a non-volatile memory device, the method comprising: applying a first program voltage to a selected word line to which memory cells are connected, in response to a program command; performing an initial program verify operation by applying an initial program verify voltage to the selected word line, in response to a suspend command or a resume command received after the suspend command; applying a second program voltage to the selected word line in response to the resume command; and performing a normal program verify operation by applying, to the selected word line, a normal program verify voltage that is different from the initial program verify voltage. ### Claim 16 (depends on 15) The method of claim 15, wherein the performing of the normal program verify operation is performed after the applying of the first program voltage or the applying of the second program voltage. ### Claim 17 (depends on 15) The method of claim 15, wherein the initial program verify voltage includes a plurality of initial program verify voltage levels respectively corresponding to a plurality of word line groups, wherein the selected word line corresponds to one of the plurality of word line groups according to a position of the selected word line. ### Claim 18 (depends on 15) The method of claim 15, wherein the initial program verify voltage includes a first initial program verify voltage level for a first word line and a second initial program verify voltage level for a second word line, wherein the first initial program verify voltage level is different from the second initial program verify voltage level, and wherein the second word line is located above the first word line. ### Claim 19 (depends on 15) The method of claim 15, wherein the suspend command is received after the normal verify operation of an N-th program loop of the program operation, wherein N is a natural number that is greater than or equal to 2, and wherein the N-th program loop includes a first program operation in which the first program voltage is applied to the selected word line and the normal verify operation. ### Claim 20 (depends on 15) The method of claim 15, wherein the suspend command is received during a bit line setup section after an N-th program loop of the program operation, wherein N is a natural number that is greater than or equal to 2, and wherein the N-th program loop includes a first program operation in which the first program voltage is applied to the selected word line and the normal verify operation.