# US 2022/0044729 A1 · Device-region layout for embedded flash

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- Number: US 2022/0044729 A1
- Document ID: US20220044729A1
- Status: Published application
- Kind: A1
- Application number: 17/506,904
- Filed: 2021-10-21
- Published: 2022-02-10
- Earliest claimed: 2018-09-27
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Shih Kuang Yang; Ping-Cheng Li; Hung-Ling Shih; Po-Wei Liu; Wen-Tuo Huang; Yu-Ling Hsu; Yong-Shiuan Tsair; Chia-Sheng Lin
- Web page: https://patentgrep.com/patent/US20220044729A1

## CPC

- G11C 16/08: Address circuits; Decoders; Word-line control circuits
- H10D 30/6892: {having at least one additional gate other than the floating gate and the control gate, e.g. program gate, erase gate or select gate}
- G11C 11/1657: {Word-line or row circuits}
- G11C 16/0433: {comprising cells containing a single floating gate transistor and one or more separate select transistors}
- H10B 12/053: {the transistor being at least partially in a trench in the substrate (vertical transistor in combination with a capacitor formed in a substrate trench H10B12/0383)}
- H10B 41/10: characterised by the top-view layout
- H10B 41/30: characterised by the memory core region
- H10D 64/035: {comprising conductor-insulator-conductor-insulator-semiconductor structures}
- H10B 41/42: Simultaneous manufacture of periphery and memory cells
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10B: ELECTRONIC MEMORY DEVICES

## Abstract

Various embodiments of the present application are directed towards an integrated memory chip with an enhanced device-region layout for reduced leakage current and an enlarged word-line etch process window (e.g., enhanced word-line etch resiliency). In some embodiments, the integrated memory chip comprises a substrate, a control gate, a word line, and an isolation structure. The substrate comprises a first source/drain region. The control gate and the word line are on the substrate. The word line is between and borders the first source/drain region and the control gate and is elongated along a length of the word line. The isolation structure extends into the substrate and has a first isolation-structure sidewall. The first isolation-structure sidewall extends laterally along the length of the word line and underlies the word line.

## Claims

### Claim 1

An integrated chip comprising:
a substrate;
a first source/drain region and a second source/drain region in the substrate;
an erase gate, a control gate, and a word line overlying the substrate, wherein the erase gate overlies the first source/drain region, wherein the word line borders the second source/drain region, and wherein the control gate is between and borders the erase gate and the word line; and
a trench isolation structure extending into the substrate, wherein the trench isolation structure is between the first and second source/drain regions, and is closer to the second source/drain region than the first source/drain region, along an axis.

### Claim 2 (depends on 1)

The integrated chip according to claim 1, wherein the trench isolation structure is spaced from the first and second source/drain regions.

### Claim 3 (depends on 1)

The integrated chip according to claim 1, wherein the erase gate, the control gate, and the word line are elongated in parallel in a direction transverse to the axis.

### Claim 4 (depends on 1)

The integrated chip according to claim 1, wherein the trench isolation structure has a first sidewall and a second sidewall both underlying the word line and respectively facing in opposite directions along the axis, and wherein the trench isolation structure is continuous along the axis from the first sidewall to the second sidewall.

### Claim 5 (depends on 4)

The integrated chip according to claim 4, wherein the trench isolation structure has a third sidewall underlying the control gate and facing a same direction as the second sidewall, and wherein the trench isolation structure is continuous along a second axis parallel with the axis from the first sidewall to the third sidewall.

### Claim 6 (depends on 1)

The integrated chip according to claim 1, wherein the trench isolation structure underlies the word line, but not the control gate, along the axis.

### Claim 7 (depends on 1)

The integrated chip according to claim 1, wherein the axis overlaps with a portion of the trench isolation structure having a T-shaped top geometry.

### Claim 8

An integrated chip comprising:
a substrate;
a pair of erase gates over the substrate;
a pair of control gates over the substrate, wherein the control gates are between and respectively border the erase gates;
a pair of word lines over the substrate, wherein the word lines are between and respectively border the control gates;
a source/drain region in the substrate, wherein the source/drain region is between and borders the word lines; and
a trench isolation structure in the substrate and extending in a closed path around the source/drain region, wherein the closed path is localized between the control gates.

### Claim 9 (depends on 8)

The integrated chip according to claim 8, wherein the closed path repeats along a length of the word lines.

### Claim 10 (depends on 8)

The integrated chip according to claim 8, wherein the closed path demarcates a device region of the substrate having a rectangular top geometry.

### Claim 11 (depends on 8)

The integrated chip according to claim 8, wherein the closed path is localized between the word lines.

### Claim 12 (depends on 8)

The integrated chip according to claim 8, wherein the substrate has a pair of sidewalls adjoining the closed path, and wherein the sidewalls respectively face opposite directions transverse to a length of the word lines.

### Claim 13 (depends on 12)

The integrated chip according to claim 12, wherein the sidewalls respectively underlie the word lines.

### Claim 14 (depends on 8)

The integrated chip according to claim 8, wherein the pair of control gates comprises a first control gate with a sidewall protrusion that overlaps with the closed path, and wherein the sidewall protrusion forms a contact pad.

### Claim 15

An integrated chip comprising:
a substrate; and
an erase gate, a control gate, and a word line overlying the substrate and laterally elongated in parallel in a first direction, wherein the control gate is between and borders the erase gate and the word line, and wherein the control gate and the word line respectively have a control-gate sidewall and a word-line sidewall facing away from the erase gate;
wherein the substrate has a substrate sidewall that faces in a second direction transverse to the first direction and that is laterally offset from and between the word-line and control-gate sidewalls, and wherein the second direction extends away from the erase gate.

### Claim 16 (depends on 15)

The integrated chip according to claim 15, wherein the substrate sidewall underlies the word line.

### Claim 17 (depends on 15)

The integrated chip according to claim 15, further comprising:
a floating gate underlying the control gate, wherein the floating gate has a floating-gate sidewall facing away from the erase gate, and wherein the substrate sidewall is laterally offset from and between the word-line and floating-gate sidewalls.

### Claim 18 (depends on 15)

The integrated chip according to claim 15, further comprising:
a trench isolation structure extending into the substrate and demarcating an H-shaped portion of the substrate that repeats along a length of the erase gate;
wherein the substrate sidewall is a sidewall of the H-shaped portion.

### Claim 19 (depends on 15)

The integrated chip according to claim 15, wherein the erase gate has a first erase-gate segment and a second erase-gate segment separated by a gap in the first direction, and wherein the control-gate sidewall, the word-line sidewall, the gap, and the substrate sidewall overlap with a common axis extending transverse to the first direction.

### Claim 20 (depends on 15)

The integrated chip according to claim 15, wherein the substrate has a second substrate sidewall that faces the substrate sidewall and underlies the word line, and wherein a contact via overlies and extends from the word line at a location laterally between the substrate sidewall and the second substrate sidewall.