# US 2022/0044720 A1 · Staggering refresh address counters of a number of memory devices, and related methods, devices, and systems > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2022/0044720 A1 - Document ID: US20220044720A1 - Status: Published application - Kind: A1 - Application number: 17/387,428 - Filed: 2021-07-28 - Published: 2022-02-10 - Earliest claimed: 2020-08-06 - Assignees: Micron Technology, Inc. - Applicants: Micron Technology, Inc. - Inventors: Christopher G. Wieduwilt; James S. Rehmeyer - Web page: https://patentgrep.com/patent/US20220044720A1 ## CPC - G11C 5/04: Supports for storage elements {, e.g. memory modules}; Mounting or fixing of storage elements on such supports - G11C 11/406: Management or control of the refreshing or charge-regeneration cycles - G11C 11/40603: {Arbitration, priority and concurrent access to memory cells for read/write or refresh operations} - G11C 11/40618: {Refresh operations over multiple banks or interleaving} - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract Methods of operating a number of memory devices are disclosed. A method may include receiving, at each of a number of memory devices, a refresh command. The method may also include refreshing, at each of the number of memory devices and in response to the refresh command, a number of memory cells based on a count of an associated refresh address counter, wherein a count of a refresh address counter of at least one memory device of the number of memory devices is offset from a count of a refresh address counter of at least one other memory device of the number of memory devices. Related systems and memory modules are also described. ## Claims ### Claim 1 A method, comprising: receiving, at each of a number of memory devices, a refresh command; and refreshing, at each of the number of memory devices and in response to the refresh command, a number of memory cells based on a count of an associated refresh address counter, a count of a refresh address counter of at least one memory device of the number of memory devices being offset from a count of a refresh address counter of at least one other memory device of the number of memory devices. ### Claim 2 (depends on 1) The method of claim 1, further comprising adjusting the count of the refresh address counter of the at least one memory device such that the count of the refresh address counter of the at least one memory device is offset from the count of the refresh address counter of the at least one other memory device. ### Claim 3 (depends on 1) The method of claim 1, further comprising incrementing an associated count of a refresh address counter of each memory device of the number of memory devices in response to refreshing the number of memory cells. ### Claim 4 (depends on 1) The method of claim 1, further comprising adjusting an associated count of a refresh address counter of more than one memory device of the number of memory devices such that a device-to-device counter offset amongst the number of memory devices is equal. ### Claim 5 (depends on 1) The method of claim 1, further comprising adjusting the count of the refresh address counter of the at least one memory device responsive to a boot or a reboot operation. ### Claim 6 (depends on 1) The method of claim 1, further comprising programming, at each of the number of memory devices, one or more fuse settings. ### Claim 7 (depends on 6) The method of claim 6, further comprising adjusting, at the at least one memory device, an initial count of the associated refresh address counter based on the one or more fuse settings. ### Claim 8 A method, comprising: receiving, at a first memory device and a second memory device, a refresh command; refreshing, at the first memory device and in response to the refresh command, a first number of memory cells based on a first count value of a first refresh address counter of the first memory device; and refreshing, at the second memory device and in response to the refresh command, a second number of memory cells of the second memory device based on a second, different count value of a second refresh address counter of the second memory device. ### Claim 9 (depends on 8) The method of claim 8, further comprising adjusting at least one of the first count value of the first memory device or the second, different count value of the second memory device such that the first count value of the first memory device is offset from the second, different count value of the second memory device. ### Claim 10 (depends on 8) The method of claim 8, further comprising: receiving the refresh command at a third memory device; and refreshing, at the third memory device and in response to the refresh command, a third number of memory cells based on a third count value of a third refresh address counter of the third memory device, wherein the third count value is different from at least one of the first count value or the second, different count value. ### Claim 11 (depends on 8) The method of claim 8, further comprising setting, at the first memory device, one or more fuses such that the first count value of the first memory device is offset from the second, different count value of the second memory device. ### Claim 12 A memory module, comprising: a number of memory devices, wherein each memory device of the number of memory devices includes: a counter having an index, wherein at least one memory device of the number of memory devices includes an index that is different from an index of at least one other memory device of the number of memory devices; and a controller configured to refresh, based on the index of the counter, a number of memory cells. ### Claim 13 (depends on 12) The memory module of claim 12, wherein the controller is further configured to adjust an index of one or more memory devices of the number of memory devices based on one or more fuse settings. ### Claim 14 (depends on 12) The memory module of claim 12, wherein an index of each device of the number of memory devices is offset from at least one other device by the same offset value. ### Claim 15 (depends on 12) The memory module of claim 12, wherein the controller is further configured to: receive a refresh command; identify a row including the number of memory cells based on the index of the memory device; and activate the row to refresh the number of memory cells. ### Claim 16 A system comprising: at least one processor device; and a number of memory devices operably coupled to the at least one processor device, wherein at least one memory device of the number of memory devices comprises a refresh address counter having a count value offset from a count value of a refresh address counter of at least one other memory device of the number of memory devices. ### Claim 17 (depends on 16) The system of claim 16, further comprising fuse circuitry, wherein the count value of the at least one memory device is programmable via one or more fuses of the fuse circuitry. ### Claim 18 (depends on 17) The system of claim 17, wherein each memory device of the number of memory devices is coupled to dedicated fuse circuitry for programming an associated count value. ### Claim 19 (depends on 16) The system of claim 16, wherein each memory device of the number of memory devices comprises a refresh address counter having a count value offset from a count value of a refresh address counter of every other memory device of the number of memory devices. ### Claim 20 (depends on 16) The system of claim 16, wherein the at least one memory device is configured to adjust its count value in response to a boot or a reboot operation and based on one or more associated fuse settings.