# US 2022/0044718 A1 · Stt-sot hybrid magnetoresistive element and manufacture thereof

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- Number: US 2022/0044718 A1
- Document ID: US20220044718A1
- Status: Published application
- Kind: A1
- Application number: 17/509,014
- Filed: 2021-10-24
- Published: 2022-02-10
- Earliest claimed: 2021-10-24
- Inventors: YIMIN GUO; RONGFU XIAO; JUN CHEN
- Web page: https://patentgrep.com/patent/US20220044718A1

## CPC

- G11C 11/161: {details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell}
- G11B 5/3909: {Arrangements using a magnetic tunnel junction}
- G11C 11/1659: {Cell access}
- G11C 11/1675: {Writing or programming circuits or methods}
- G11C 11/18: using Hall-effect devices
- H01F 10/3286: {Spin-exchange coupled multilayers having at least one layer with perpendicular magnetic anisotropy}
- H01F 41/307: {insulating or semiconductive spacer}
- H10B 61/22: {of the field-effect transistor [FET] type}
- H10N 50/01: Manufacture or treatment
- H10N 50/10: Magnetoresistive devices
- H10N 50/85: Materials of the active region
- H10N 52/01: Manufacture or treatment
- H10N 52/80: Constructional details
- H10B 61/20: {comprising components having three or more electrodes, e.g. transistors}
- G11C: STATIC STORES (semiconductor memory devices H10B)
- G11B: INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER (recording measured values in a way that does not require playback through a transducer G01D9/00; recording or playback apparatus using mechanically marked tape, e.g. punched paper tape, or using unit records, e.g. punched or magnetically marked cards G06K; transferring data from one type of record carrier to another G06K1/18; circuits for coupling output of reproducer to radio receiver H04B1/20; gramophone pick-ups or like acoustic electromechanical transducers or circuits therefor H04R)
- H01F: MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
- H10B: ELECTRONIC MEMORY DEVICES
- H10N: ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR

## Abstract

A magnetoresistive element comprises a nonmagnetic sidewall-current-channel (SCC) structure provided on a surface of the SOT material layer that exhibits the Spin Hall Effect, which is opposite to a surface of the SOT material layer where the magnetic recording layer is provided, and comprising an insulating medium in a central region of the SCC structure, and a conductive medium being a sidewall of the SCC structure and surrounding the insulating medium, making an electric current crowding inside the SOT material layer and the magnetic recording layer to achieve a spin-orbit torque and a higher spin-polarization degree for an applied electric current.

## Claims

### Claim 1

A magnetoresistive element comprising:
a magnetic reference layer having a perpendicular magnetic anisotropy and having an invariable magnetization direction;
a tunnel barrier layer provided on the magnetic reference layer;
a magnetic recording layer provided on the tunnel barrier layer and having a perpendicular magnetic anisotropy and a variable magnetization direction;
an SOT material layer provided on the magnetic recording layer, wherein the SOT material layer comprises one or more materials that exhibit the Spin Hall Effect (SHE);
a sidewall-current-channel (SCC) structure provided on the SOT material layer, wherein the SCC structure comprises an insulating medium in a central region of the SCC structure, and a conductive medium being a vertical sidewall of the SCC structure and surrounding the insulating medium;
a protective cap layer provided on the insulating medium; and
a hard mask layer provided on the protective cap layer;
wherein the tunnel barrier layer has a first resistance-area product (RAO, the insulating medium comprises an insulating oxide or nitride material and has a second resistance-area product (RA2), the second resistance-area product (RA2) is higher than the first resistance-area product (RAO, the insulating medium comprises an electrically insulating material, the conductive medium comprises an electrically conductive material making electrical connection between the SOT material layer and the protective cap layer.

### Claim 2 (depends on 1)

The element of claim 1, wherein said conductive medium further extends along a vertical direction to be vertical sidewalls of said protective cap layer and said hard mask layer, and surrounds said protective cap layer and said hard mask layer.

### Claim 3 (depends on 1)

The element of claim 1, wherein said conductive medium comprises at least one layer of metal or metal alloy or conductive metal nitride material, preferred to be Ru, Mo, W, Ta, Ti, Cr, V, Hf, Nb, Zr, Fe, Co, Ni, Cu, Pt, Au, Ag, Rh, Ir, Os, Re, B, Al, or alloy thereof, or nitride thereof, and has a wall thickness between 1.5 nm and 5.0 nm.

### Claim 4 (depends on 1)

The element of claim 1, wherein said insulating medium comprises at least one layer of oxide or nitride, preferred to be selected from the group consisting of MgO, MgAl2O4, Al2O3, HfO2, ZrO2, TiO2, SiO2, Y2O3, RuO, OsO, TcO, ReO, BeO, SiN, RuN, OsN, TcN, ReN, NiO, CoO, FeO, FeCoO2, NiFeO2, CoNiO2, MnO, CrO, VO, TiO, ZnO and CdO.

### Claim 5 (depends on 1)

The element of claim 1, wherein said second resistance-area product (RA2) is at least 5 times said first resistance-area product (RAO.

### Claim 6 (depends on 1)

The element of claim 1, wherein said SOT material layer comprises a metal or metal alloy comprising one or more of Pt, Pd, Au, Ag and Cu, or comprises a metal or metal alloy comprising one or more of Pt, Pd, Au, Ag and Cu, doped with elements including one or more of Ir, Bi, Ti, S, Ta, W, Hf, Mo, Se, B, Sb, Re, La, C, P, La, As, Sc, O, Ga, Al, Y, In, Ce, Pr, Nd, F, Mn and Sr.

### Claim 7 (depends on 6)

The element of claim 6, wherein said SOT material layer further comprises a thin layer comprising one or more of Ir, Bi, Ti, S, Ta, W, Hf, Mo, Se, B, Sb, Re, La, C, P, La, As, Sc, O, Ga, Al, Y, In, Ce, Pr, Nd, F, Mn and Sr.

### Claim 8 (depends on 1)

The element of claim 1, further comprising a performance enhancement layer between said magnetic recording layer and said SOT material layer, wherein said performance enhancement layer comprises at least one layer of Ru, Mg, Mo, W, Ta, Ti, Cr, V, Hf, Nb, Zr, Fe, Co, Ni, Al, Cu, Pt, Au, Ag, Rh, Ir, Os, Re, or alloy thereof, or oxide thereof.

### Claim 9 (depends on 1)

The element of claim 1, further comprising an upper electrode and a lower electrode which sandwich said magnetoresistive element, and further comprising a write circuit which bi-directionally supplies a current to said magnetoresistive element, and a select transistor electrically connected between said magnetoresistive elements and said write circuit.

### Claim 10

A method of manufacturing a perpendicular magnetic tunnel junction (put) element having a sidewall-current-channel (SCC) structure for being used in a magnetic memory device, the method comprising the steps of:
providing a bottom electrode;
depositing an MTJ stack over the bottom electrode, wherein the MTJ stack comprises at least a magnetic reference layer, a tunnel barrier layer provided on a top surface of the magnetic reference layer and a magnetic recording layer provided on a top surface of the tunnel barrier layer;
depositing an SOT material layer over the MTJ stack;
depositing an insulating medium layer over the SOT material layer;
depositing a protective cap layer over the insulating medium layer;
depositing a hard mask layer over the protective cap layer;
conducting a photolithographic process to form a patterned hard mask having an opening exposed area on the protective cap layer;
first etching the protective cap layer and the insulating medium layer not covered by the patterned hard mask;
forming a conductive encapsulation layer on the top surface of the patterned hard mask, on the top surface of the etched insulating medium layer and on sidewalls of the insulating medium layer, the protective cap layer and the hard mask, wherein the conductive encapsulation layer is a conformal layer made of an electrically conductive material;
second etching away the conductive encapsulation layer on horizontal surfaces, leaving the conductive encapsulation layer on vertical sidewalls of the insulating medium layer, the protective cap layer and the hard mask, wherein sidewalls of the insulating medium layer are covered by the conductive encapsulation layer forming a conductive medium electrically connecting the SOT material layer and the protective cap layer;
third etching the SOT material layer and the MTJ stack to form a plurality of MTJ cells; and
forming a dielectric encapsulation layer on the top surface of the patterned hard mask and on sidewalls of the MTJ stack and the conductive encapsulation layer, wherein the dielectric encapsulation layer is made of an electrically insulating material.

### Claim 11 (depends on 10)

The element of claim 10, wherein said conductive medium comprises at least one layer of metal or metal alloy or conductive metal nitride material, preferred to be Ru, Mo, W, Ta, Ti, Cr, V, Hf, Nb, Zr, Fe, Co, Ni, Cu, Pt, Au, Ag, Rh, Ir, Os, Re, B, Al, or alloy thereof, or nitride thereof.

### Claim 12 (depends on 10)

The element of claim 10, wherein said insulating medium layer has a thickness of at least 12 angstroms and comprises at least one layer of oxide or nitride, preferred to be selected from the group consisting of MgO, MgAl2O4, Al2O3, HfO2, ZrO2, TiO2, SiO2, Y2O3, RuO, OsO, TcO, ReO, BeO, SiN, RuN, OsN, TcN, ReN, NiO, CoO, FeO, FeCoO2, NiFeO2, CoNiO2, MnO, CrO, VO, TiO, ZnO and CdO.

### Claim 13 (depends on 10)

The element of claim 10, wherein said SOT material layer is made from one or more materials that exhibit the Spin Hall Effect to a thickness from 1.5 nm to 10 nm, preferred to be selected from the group consisting of Pt, Pd, Au, Ag, Cu, or alloys thereof, or alloys thereof being doped with Ta, W, Hf, Ir, Bi, Se or oxygen, or a noble metal being doped with Ta, W, Hf, Ir, Bi, Se or oxygen, or combinations thereof.

### Claim 14 (depends on 10)

The element of claim 10, wherein said first etching stops at a bottom surface of said insulating medium layer, or inside said SOT material layer, or within a lower-half portion of said insulating medium layer.

### Claim 15 (depends on 10)

The element of claim 10, further comprising, after forming said conductive encapsulation layer, forming a sacrificial encapsulation layer of a dielectric material, the dielectric material is preferred to be at least one selected from the group consisting of SiNx, SiO2, SiOxNy, SiC, SiCN and amorphous Carbon.

### Claim 16 (depends on 10)

The element of claim 10, wherein said second etching comprises a vertical etching using collimated reactive ion beam or collimated ion beam to remove said conductive encapsulation layer on horizontal surfaces.

### Claim 17 (depends on 10)

The element of claim 10, further comprising, after depositing said MTJ stack, forming a performance enhancement layer, wherein said performance enhancement layer comprises at least one layer of Ru, Mg, Mo, W, Ta, Ti, Cr, V, Hf, Nb, Zr, Fe, Co, Ni, Al, Cu, Pt, Au, Ag, Rh, Ir, Os, Re, or alloy thereof, or oxide thereof.

### Claim 18 (depends on 10)

The element of claim 10, further comprising, after forming said dielectric encapsulation layer, refilling a dielectric layer, conducting a CMP process and forming a top electrode.

### Claim 19

A method of manufacturing a magnetic tunnel junction element having a sidewall-current-channel (SCC) structure for being used in a magnetic memory device, the method comprising the steps of:
providing a bottom electrode;
depositing an MTJ stack over the bottom electrode, wherein the MTJ stack comprises at least a magnetic reference layer, a tunnel barrier layer provided on a top surface of the magnetic reference layer, and a magnetic recording layer provided on a top surface of the tunnel barrier layer;
depositing an SOT material layer over the MTJ stack, the SOT material layer exhibiting the Spin Hall Effect;
depositing an insulating medium layer over the SOT material layer;
depositing a protective cap layer over the insulating medium layer;
depositing a hard mask layer over the protective cap layer;
conducting a photolithographic process to form a patterned hard mask having an opening exposed area on the protective cap layer;
first etching the protective cap layer, the insulating medium layer, the SOT material layer, and the MTJ stack not covered by the patterned hard mask;
forming an insulating encapsulation layer on the top surface of the patterned hard mask, on the top surface of the etched insulating medium layer and on sidewalls of the MTJ stack, the SOT material layer, the insulating medium layer, the protective cap layer and the hard mask, wherein the insulating encapsulation layer is a conformal layer made of a dielectric material;
depositing a first dielectric layer over the insulating encapsulation layer;
conducting a first CMP process and stopping at the top surface of the patterned hard mask;
second etching the insulating encapsulation layer and the first dielectric layer not covered by the patterned hard mask, and stopping at a vertical level being higher than a top surface of the magnetic recording layer and exposing at least a top portion of the SOT material layer;
forming a conductive encapsulation layer on the top surface of the patterned hard mask, on the top surface of the etched insulating encapsulation layer and the etched first dielectric layer and on sidewalls of the SOT material layer, the insulating medium layer, the protective cap layer and the hard mask, wherein the conductive encapsulation layer is a conformal layer made of an electrically conductive material;
third etching away the conductive encapsulation layer on horizontal surfaces, leaving the conductive encapsulation layer on vertical sidewalls of the SOT material layer, the insulating medium layer, the protective cap layer and the hard mask, wherein sidewalls of the insulating medium layer are covered by the conductive encapsulation layer forming a conductive medium electrically connecting the SOT material layer and the protective cap layer;
depositing a second dielectric layer;
conducting a second CMP process; and
forming a top electrode.

### Claim 20 (depends on 19)

The element of claim 19, further comprising, after depositing said MTJ stack, forming a performance enhancement layer, wherein said performance enhancement layer comprises at least one layer of Ru, Mg, Mo, W, Ta, Ti, Cr, V, Hf, Nb, Zr, Fe, Co, Ni, Al, Cu, Pt, Au, Ag, Rh, Ir, Os, Re, or alloy thereof, or oxide thereof.