# US 2022/0044716 A1 · Semiconductor device

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- Number: US 2022/0044716 A1
- Document ID: US20220044716A1
- Status: Published application
- Kind: A1
- Application number: 17/195,294
- Filed: 2021-03-08
- Published: 2022-02-10
- Earliest claimed: 2020-08-04
- Assignees: SK hynix Inc.
- Applicants: SK hynix Inc.
- Inventors: Woongrae KIM
- Web page: https://patentgrep.com/patent/US20220044716A1

## CPC

- G11C 7/12: Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
- G11C 7/222: {Clock generating, synchronizing or distributing circuits within memory device}
- G11C 7/1096: {Write circuits, e.g. I/O line write drivers}
- G11C 7/22: Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

A semiconductor device includes an operation flag generation circuit configured to generate an operation flag at a time when a flag period elapses from a time when an internal setting signal is generated to perform a write operation accompanied by an auto-precharge operation; and an auto-precharge pulse generation circuit configured to generate an auto-precharge pulse by shifting the operation flag by a pulse generation period set by a period code based on divided clocks generated by dividing an internal clock.

## Claims

### Claim 1

A semiconductor device comprising:
an operation flag generation circuit configured to generate an operation flag at a time when a flag period elapses from a time when an internal setting signal is generated to perform a write operation accompanied by an auto-precharge operation; and
an auto-precharge pulse generation circuit configured to generate an auto-precharge pulse by shifting the operation flag by a pulse generation period set by a period code based on divided clocks, the divided clocks generated by dividing an internal clock.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, further comprising:
a setting signal input circuit configured to generate the internal setting signal based on a chip select signal, a clock, and a setting signal.

### Claim 3 (depends on 1)

The semiconductor device of claim 1, wherein the operation flag generation circuit sets the flag period based on a write latency and a burst length.

### Claim 4 (depends on 1)

The semiconductor device of claim 1, further comprising:
a divided clock generation circuit configured to generate the divided clocks, the divided clocks including a first divided clock which is generated by dividing the internal clock, a second divided clock which is generated by dividing the first divided clock, and a third divided clock which is generated by dividing the second divided clock.

### Claim 5 (depends on 4)

The semiconductor device of claim 4, wherein the divided clock generation circuit resets the second divided clock and the third divided clock when the operation flag is generated.

### Claim 6 (depends on 4)

The semiconductor device of claim 4, wherein the auto-precharge pulse generation circuit comprises:
a shifting control signal generation circuit configured to generate a quotient code and a remainder code based on the pulse generation period.

### Claim 7 (depends on 6)

The semiconductor device of claim 6, wherein the shifting control signal generation circuit calculates a quotient and a remainder by dividing the pulse generation period by a value set to a multiple of a cycle period of the third divided clock, generates the quotient code corresponding to the quotient, and generates the remainder code corresponding to the remainder.

### Claim 8 (depends on 6)

The semiconductor device of claim 6, wherein the auto-precharge pulse generation circuit further comprises:
a pre-shifting circuit configured to generate a shifting operation flag by shifting the operation flag by a pre-shifting period set based on the remainder code, in synchronization with the first divided clock.

### Claim 9 (depends on 8)

The semiconductor device of claim 8, wherein the pre-shifting circuit comprises:
a pre-shifting pulse generation circuit configured to generate a pre-shifting pulse by shifting the operation flag in synchronization with the first divided clock; and
a pre-selection circuit configured to output one of the operation flag and the pre-shifting pulse as a pre-selection pulse based on the remainder code.

### Claim 10 (depends on 8)

The semiconductor device of claim 8, wherein the auto-precharge pulse generation circuit further comprises:
a shifting circuit configured to generate the auto-precharge pulse by shifting the shifting operation flag by a shifting period set based on the quotient code, in synchronization with the third divided clock.

### Claim 11 (depends on 10)

The semiconductor device of claim 10, wherein the shifting circuit comprises:
a shifting pulse generation circuit configured to generate a shifting pulse by shifting the shifting operation flag in synchronization with the third divided clock; and
a selection circuit configured to output one of the shifting operation flag and the shifting pulse as a selection pulse based on the quotient code.

### Claim 12

A semiconductor device comprising:
a shifting control signal generation circuit configured to generate a quotient code and a remainder code based on a pulse generation period;
a pre-shifting circuit configured to generate a shifting operation flag by shifting an operation flag by a pre-shifting period set based on the remainder code, in synchronization with a first divided clock; and
a shifting circuit configured to generate an auto-precharge pulse by shifting the shifting operation flag by a shifting period set based on the quotient code, in synchronization with a third divided clock.

### Claim 13 (depends on 12)

The semiconductor device of claim 12, further comprising:
a divided clock generation circuit configured to generate the first divided clock, a second divided clock, and the third divided clock, the first divided clock being generated by dividing an internal clock, the second divided clock being generated by dividing the first divided clock and the third divided clock being generated by dividing the second divided clock.

### Claim 14 (depends on 13)

The semiconductor device of claim 13, wherein the divided clock generation circuit resets the second divided clock and the third divided clock when the operation flag is generated.

### Claim 15 (depends on 12)

The semiconductor device of claim 12, further comprising:
an operation flag generation circuit configured to generate the operation flag at a time when a flag period elapses from a time when an internal setting signal is generated to perform a write operation accompanied by an auto-precharge operation.

### Claim 16 (depends on 15)

The semiconductor device of claim 15, wherein the operation flag generation circuit sets the flag period based on a write latency and a burst length.

### Claim 17 (depends on 15)

The semiconductor device of claim 15, further comprising:
a setting signal input circuit configured to generate the internal setting signal based on a chip select signal, a clock, and a setting signal.

### Claim 18 (depends on 12)

The semiconductor device of claim 12, wherein the shifting control signal generation circuit calculates a quotient and a remainder by dividing the pulse generation period by a value set to a multiple of a cycle period of the third divided clock, generates the quotient code corresponding to the quotient, and generates the remainder code corresponding to the remainder.

### Claim 19 (depends on 12)

The semiconductor device of claim 12, wherein the pre-shifting circuit comprises:
a pre-shifting pulse generation circuit configured to generate a pre-shifting pulse by shifting the operation flag in synchronization with the first divided clock; and
a pre-selection circuit configured to output one of the operation flag and the pre-shifting pulse as a pre-selection signal based on the remainder code.

### Claim 20 (depends on 12)

The semiconductor device of claim 12, wherein the shifting circuit comprises:
a shifting pulse generation circuit configured to generate a shifting pulse by shifting the shifting operation flag in synchronization with the third divided clock; and
a selection circuit configured to output one of the shifting operation flag and the shifting pulse as a selection signal based on the quotient code.