# US 2022/0044708 A1 · Storage device having multiple storage dies and identification method > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2022/0044708 A1 - Document ID: US20220044708A1 - Status: Published application - Kind: A1 - Application number: 17/413,600 - Filed: 2019-11-21 - Published: 2022-02-10 - Earliest claimed: 2018-12-20 - Assignees: Huizhou Tcl Mobile Communication Co., Ltd. - Applicants: HuiZhou TCL Mobile Communication Co., Ltd. - Inventors: Gaoxiang ZOU - Web page: https://patentgrep.com/patent/US20220044708A1 ## CPC - G11C 5/025: {Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device (geometrical lay-out of the components in integrated circuits, geometrical lay-out of the components in integrated circuits H10D89/10)} - G11C 11/4072: Circuits for initialization, powering up or down, clearing memory or presetting - G11C 11/419: Read-write [R-W] circuits - G06F 12/0284: {Multiple user address space allocation, e.g. using different base addresses (interprocessor communication G06F15/163)} - G06F 12/0646: {Configuration or reconfiguration} - G11C 5/04: Supports for storage elements {, e.g. memory modules}; Mounting or fixing of storage elements on such supports - G11C 7/1063: {Control signal output circuits, e.g. status or busy flags, feedback command signals} - G11C 2207/105: Aspects related to pads, pins or terminals - G11C: STATIC STORES (semiconductor memory devices H10B) - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract A storage device having multiple storage dies is disclosed. The storage device comprises: a printed circuit board having a main surface, a plurality of universal input/output pins, placed on the main surface of the printed circuit board, and a plurality of random access storage dies, corresponding to the plurality of universal input/output pins, placed on the plurality of universal input/output pins. ## Claims ### Claim 1 A storage device having multiple storage dies, the storage device comprising: a printed circuit board, having a main surface; a plurality of universal input/output pins, placed on the main surface of the printed circuit board; and a plurality of random access storage dies, corresponding to the plurality of universal input/output pins, placed on the plurality of universal input/output pins. ### Claim 2 (depends on 1) The storage device of claim 1, wherein a number of the plurality of universal input/output pins is not less than 2. ### Claim 3 (depends on 1) The storage device of claim 1, wherein a number of the plurality of random access storage dies is not less than 2 and is corresponding to a number of the plurality of universal input/output pins. ### Claim 4 (depends on 1) The storage device of claim 1, wherein the plurality of random access storage dies have a same material removal rate. ### Claim 5 (depends on 1) The storage device of claim 1, wherein the plurality of random access storage dies comprise dies having a same memory timing, dies having different memory dies, or any combination. ### Claim 6 An identification method, used in an embedded equipment having a storage device having multiple storage dies, the embedded equipment comprising a processing unit and a synchronous dynamic random access memory device, the identification method comprising: establishing a memory timing look-up table and storing the memory timing look-up table in the synchronous dynamic random access memory device; establishing a dynamic random access memory type mapping table, and storing the dynamic random access memory type mapping table in the synchronous dynamic random access memory device; utilizing the processing unit to check a number of universal input/output pins of the storage device having multiple storage dies; utilizing the processing unit to preload and initiate voltage levels of the universal input/output pins; utilizing the processing unit to obtain a composite voltage level information of the universal input/output pins and obtaining a dynamic random access memory type through the dynamic random access memory type mapping table; utilizing the processing unit to obtain a memory timing number of a random access storage device through the memory timing look-up table according to the dynamic random access memory type; and utilizing the processing unit to initialize the random access storage device according to the memory timing number to complete an identification operation. ### Claim 7 (depends on 6) The identification method of claim 6, wherein the step of establishing the memory timing look-up table and storing the memory timing look-up table in the synchronous dynamic random access memory device comprises: establishing the memory timing look-up table through a memory timing of the dynamic random access memory type. ### Claim 8 (depends on 6) The identification method of claim 6, wherein the step of establishing the dynamic random access memory type mapping table and storing the dynamic random access memory type mapping table in the synchronous dynamic random access memory device comprises: establishing the dynamic random access memory type mapping table according to a relationship between the composite voltage level information of the universal input/output pins and the dynamic random access memory device. ### Claim 9 (depends on 6) The identification method of claim 6, wherein the step of utilizing the processing unit to check a number of universal input/output pins of the storage device comprises: placing the number of the storage dies on the universal input/output pins. ### Claim 10 (depends on 6) The identification method of claim 6, wherein the step of utilizing the processing unit to preload and initiate voltage levels of the universal input/output pins comprising: utilizing the processing unit to initiate the voltage levels of the universal input/output pins to make the voltage levels being with 0 dB or 0 Np. ### Claim 11 A storage medium, storing a plurality of instructions, configured to be executed by a processing unit to perform operations comprising: establishing a memory timing look-up table and storing the memory timing look-up table in the synchronous dynamic random access memory device; establishing a dynamic random access memory type mapping table, and storing the dynamic random access memory type mapping table in the synchronous dynamic random access memory device; utilizing the processing unit to check a number of universal input/output pins of the storage device having multiple storage dies; utilizing the processing unit to preload and initiate voltage levels of the universal input/output pins; utilizing the processing unit to obtain a composite voltage level information of the universal input/output pins and obtaining a dynamic random access memory type through the dynamic random access memory type mapping table; utilizing the processing unit to obtain a memory timing number of a random access storage device through the memory timing look-up table according to the dynamic random access memory type; and utilizing the processing unit to initialize the random access storage device according to the memory timing number to complete an identification operation. ### Claim 12 (depends on 11) The storage medium of claim 11, wherein the operation of establishing the memory timing look-up table and storing the memory timing look-up table in the synchronous dynamic random access memory device comprises: establishing the memory timing look-up table through a memory timing of the dynamic random access memory type. ### Claim 13 (depends on 11) The storage medium of claim 11, wherein the operation of establishing the dynamic random access memory type mapping table and storing the dynamic random access memory type mapping table in the synchronous dynamic random access memory device comprises: establishing the dynamic random access memory type mapping table according to a relationship between the composite voltage level information of the universal input/output pins and the dynamic random access memory device. ### Claim 14 (depends on 11) The storage medium of claim 11, wherein the operation of utilizing the processing unit to check a number of universal input/output pins of the storage device comprises: placing the number of the storage dies on the universal input/output pins. ### Claim 15 (depends on 11) The storage medium of claim 11, wherein the operation of utilizing the processing unit to preload and initiate voltage levels of the universal input/output pins comprising: utilizing the processing unit to initiate the voltage levels of the universal input/output pins to make the voltage levels being with 0 dB or 0 Np. ### Claim 16 (depends on 1) The storage device of claim 1 being a random access memory (RAM). ### Claim 17 (depends on 1) The storage device of claim 1 being a dynamic random access memory (DRAM). ### Claim 18 (depends on 1) The storage device of claim 1 being a static random access memory (SRAM). ### Claim 19 (depends on 6) The identification method of claim 6, wherein the storage device is a dynamic random access memory (DRAM). ### Claim 20 (depends on 6) The identification method of claim 6, wherein the storage device is a static random access memory (SRAM).