# US 2022/0044652 A1 · Data interface device and method of display apparatus

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- Number: US 2022/0044652 A1
- Document ID: US20220044652A1
- Status: Published application
- Kind: A1
- Application number: 17/388,534
- Filed: 2021-07-29
- Published: 2022-02-10
- Earliest claimed: 2020-08-04
- Assignees: LG Display Co., Ltd.
- Applicants: LG Display Co., Ltd.
- Inventors: Yang Seok JEONG; Young Ho KIM; Dong In NOH
- Web page: https://patentgrep.com/patent/US20220044652A1

## CPC

- G09G 5/008: {Clock recovery}
- G09G 3/2096: {Details of the interface to the display terminal specific for a flat panel (suitable for both CRT and flat panel G09G5/006; specific for a CRT G09G1/167)}
- G09G 2310/061: for resetting or blanking
- G09G 2330/06: Handling electromagnetic interferences [EMI], covering emitted as well as received electromagnetic radiation
- G09G 2370/08: Details of image data interface between the display device controller and the data line driver circuit
- G09G 2370/10: Use of a protocol of communication by packets in interfaces along the display data pipeline
- G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00)

## Abstract

Disclosed herein is a data interface device of a display apparatus including a timing controller, encoding clock-embedded image data corresponding to a logic high period of a data enable signal and clock-embedded blank data corresponding to a logic low period of the data enable signal and transferring an encoded data transfer packet to a transfer line, and a source integrated circuit generating an internal clock based on the encoded data transfer packet received through the transfer line and selectively decoding the clock-embedded image data based on the internal clock, wherein a transition pattern of the clock-embedded blank data differs in a plurality of transfer lines.

## Claims

### Claim 1

A data interface device of a display apparatus, the data interface device comprising:
a first transfer circuit encoding first clock-embedded image data corresponding to a logic high period of a data enable signal and first clock-embedded blank data corresponding to a logic low period of the data enable signal and transferring an encoded first data transfer packet to a first transfer line;
a first reception circuit generating a first internal clock based on the encoded first data transfer packet received through the first transfer line and decoding the first clock-embedded image data based on the first internal clock;
a second transfer circuit encoding second clock-embedded image data corresponding to the logic high period of the data enable signal and second clock-embedded blank data corresponding to the logic low period of the data enable signal and transferring an encoded second data transfer packet to a second transfer line; and
a second reception circuit generating a second internal clock based on the encoded second data transfer packet received through the second transfer line and decoding the second clock-embedded image data based on the second internal clock,
wherein a first transition pattern of the first clock-embedded blank data differs from a second transition pattern of the second clock-embedded blank data.

### Claim 2 (depends on 1)

The data interface device of claim 1, wherein the first transfer circuit comprises:
a first linear feedback shifter register outputting first linear feedback information based on a first seed signal in the logic high period of the data enable signal;
a first image scramble circuit combining and scrambling first image data and the first linear feedback information to generate the first clock-embedded image data;
a second linear feedback shifter register outputting second linear feedback information based on a second seed signal differing from the first seed signal in the logic low period of the data enable signal; and
a first blank scramble circuit combining and scrambling first blank data and the second linear feedback information to generate the first clock-embedded blank data.

### Claim 3 (depends on 2)

The data interface device of claim 2, wherein the second transfer circuit comprises:
a second image scramble circuit combining and scrambling second image data and the first linear feedback information to generate the second clock-embedded image data; and
a second blank scramble circuit combining and scrambling the second linear feedback information and second blank data differing from the first blank data to generate the second clock-embedded blank data.

### Claim 4 (depends on 1)

The data interface device of claim 1, wherein the first transfer circuit comprises:
a first linear feedback shifter register outputting first linear feedback information based on a seed signal in the logic high period of the data enable signal;
a first image scramble circuit combining and scrambling first image data and the first linear feedback information to generate the first clock-embedded image data;
a second linear feedback shifter register outputting second linear feedback information without a designated seed signal in the logic low period of the data enable signal; and
a first blank scramble circuit combining and scrambling first blank data and the second linear feedback information to generate the first clock-embedded blank data.

### Claim 5 (depends on 4)

The data interface device of claim 4, wherein the second transfer circuit comprises:
a second image scramble circuit combining and scrambling second image data and the first linear feedback information to generate the second clock-embedded image data; and
a second blank scramble circuit combining and scrambling the second linear feedback information and second blank data differing from the first blank data to generate the second clock-embedded blank data.

### Claim 6 (depends on 1)

The data interface device of claim 1, wherein the first transfer circuit comprises:
a first linear feedback shifter register outputting first linear feedback information based on a first seed signal in the logic high period of the data enable signal;
a first image scramble circuit combining and scrambling first image data and the first linear feedback information to generate the first clock-embedded image data;
a second linear feedback shifter register outputting second linear feedback information based on a second seed signal differing from the first seed signal in the logic low period of the data enable signal; and
a first blank scramble circuit combining and scrambling common blank data and the second linear feedback information to generate the first clock-embedded blank data.

### Claim 7 (depends on 6)

The data interface device of claim 6, wherein the second transfer circuit comprises:
the first linear feedback shifter register;
a second image scramble circuit combining and scrambling second image data and the first linear feedback information to generate the second clock-embedded image data;
a third linear feedback shifter register outputting third linear feedback information based on a third seed signal differing from the second seed signal in the logic low period of the data enable signal; and
a second blank scramble circuit combining and scrambling the common blank data and the third linear feedback information to generate the second clock-embedded blank data.

### Claim 8 (depends on 2)

The data interface device of claim 2, wherein the second transfer circuit comprises:
a second image scramble circuit combining and scrambling second image data and the first linear feedback information to generate the second clock-embedded image data;
a third linear feedback shifter register outputting third linear feedback information based on a third seed signal differing from the second seed signal in the logic low period of the data enable signal; and
a second blank scramble circuit combining and scrambling the third linear feedback information and second blank data differing from the first blank data to generate the second clock-embedded blank data.

### Claim 9 (depends on 1)

The data interface device of claim 1, wherein
the first reception circuit selectively decodes and descrambles the first clock-embedded image data in the encoded first data transfer packet received through the first transfer line to recover first image data included in the first clock-embedded image data, and
the second reception circuit selectively decodes and descrambles the second clock-embedded image data in the encoded second data transfer packet received through the second transfer line to recover second image data included in the second clock-embedded image data.

### Claim 10 (depends on 1)

The data interface device of claim 1, wherein
the first and second transfer circuits and the first and second reception circuits are connected to a common linear feedback shifter register which outputs a same linear feedback information, and
the common linear feedback shifter register outputs common linear feedback information based on a same seed signal in the logic high period of the data enable signal.

### Claim 11

A data interface device of a display apparatus, the data interface device comprising:
a timing controller encoding clock-embedded image data corresponding to a logic high period of a data enable signal and clock-embedded blank data corresponding to a logic low period of the data enable signal and transferring an encoded data transfer packet to a transfer line; and
a source integrated circuit generating an internal clock based on the encoded data transfer packet received through the transfer line and selectively decoding the clock-embedded image data based on the internal clock,
wherein a transition pattern of the clock-embedded blank data differs in a plurality of transfer lines.

### Claim 12 (depends on 11)

The data interface device of claim 11, further comprising:
a linear feedback shifter register, outputting linear feedback information based on a seed signal in the logic low period of the data enable signal, and a first transfer circuit and a second transfer circuit respectively connected to a first transfer line and a second transfer line,
wherein the first transfer circuit comprises a first blank scramble circuit combining and scrambling first blank data and the linear feedback information to generate first clock-embedded blank data, and
wherein the second transfer circuit comprises a second blank scramble circuit combining and scrambling the linear feedback information and second blank data differing from the first blank data to generate second clock-embedded blank data including a transition pattern that differs from a transition pattern of the first clock-embedded blank data.

### Claim 13 (depends on 11)

The data interface device of claim 11, further comprising:
a linear feedback shifter register, outputting linear feedback information without a designated seed signal in the logic low period of the data enable signal, and a first transfer circuit and a second transfer circuit respectively connected to a first transfer line and a second transfer line,
wherein the first transfer circuit comprises a first blank scramble circuit combining and scrambling first blank data and the linear feedback information to generate first clock-embedded blank data, and
wherein the second transfer circuit comprises a second blank scramble circuit combining and scrambling the linear feedback information and second blank data differing from the first blank data to generate second clock-embedded blank data including a transition pattern that differs from a transition pattern of the first clock-embedded blank data.

### Claim 14 (depends on 11)

The data interface device of claim 11, further comprising:
a first transfer circuit and a second transfer circuit respectively connected to a first transfer line and a second transfer line,
wherein the first transfer circuit comprises a first linear feedback shifter register, outputting first linear feedback information based on a first seed signal in the logic low period of the data enable signal, and a first blank scramble circuit combining and scrambling common blank data and the first linear feedback information to generate first clock-embedded blank data, and
wherein the second transfer circuit comprises a second linear feedback shifter register, outputting second linear feedback information based on a second seed signal differing from the first seed signal in the logic low period of the data enable signal, and a second blank scramble circuit combining and scrambling the common blank data and the second linear feedback information to generate second clock-embedded blank data including a transition pattern that differs from a transition pattern of the first clock-embedded blank data.

### Claim 15 (depends on 11)

The data interface device of claim 11, further comprising:
a first transfer circuit and a second transfer circuit respectively connected to a first transfer line and a second transfer line,
wherein the first transfer circuit comprises a first linear feedback shifter register, outputting first linear feedback information based on a first seed signal in the logic low period of the data enable signal, and a first blank scramble circuit combining and scrambling first blank data and the first linear feedback information to generate first clock-embedded blank data, and
wherein the second transfer circuit comprises a second linear feedback shifter register, outputting second linear feedback information based on a second seed signal differing from the first seed signal in the logic low period of the data enable signal, and a second blank scramble circuit combining and scrambling the second linear feedback information and second blank data differing from the first blank data to generate second clock-embedded blank data including a transition pattern which differs from a transition pattern of the first clock-embedded blank data.

### Claim 16

A data interface method of a display apparatus, the data interface method comprising:
encoding clock-embedded image data corresponding to a logic high period of a data enable signal and clock-embedded blank data corresponding to a logic low period of the data enable signal, and transferring an encoded data transfer packet to a transfer line; and
generating an internal clock based on the encoded data transfer packet received through the transfer line and selectively decoding the clock-embedded image data based on the internal clock,
wherein a transition pattern of the clock-embedded blank data differs in a plurality of transfer lines.