# US 2022/0044634 A1 · Display panel of an organic light emitting diode display device, and organic light emitting diode display device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2022/0044634 A1 - Document ID: US20220044634A1 - Status: Published application - Kind: A1 - Application number: 17/199,851 - Filed: 2021-03-12 - Published: 2022-02-10 - Earliest claimed: 2020-08-05 - Assignees: Samsung Display Co., Ltd. - Applicants: Samsung Display Co., Ltd. - Inventors: JI-HYUN KA; NACKHYEON KEUM; KIMYEONG EOM - Web page: https://patentgrep.com/patent/US20220044634A1 ## CPC - G09G 3/3233: with pixel circuitry controlling the current through the light-emitting element - G09G 3/3258: with pixel circuitry controlling the voltage across the light-emitting element - G09G 3/3291: in which the data driver supplies a variable data voltage for setting the current through, or the voltage across, the light-emitting elements - G09G 3/3266: Details of drivers for scan electrodes - G09G 2300/0426: Layout of electrodes and connections - G09G 2300/0452: Details of colour pixel setup, e.g. pixel composed of a red, a blue and two green components - G09G 2300/0819: used for counteracting undesired variations, e.g. feedback or autozeroing - G09G 2300/0852: being a dynamic memory with more than one capacitor - G09G 2300/0861: with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes - G09G 2300/0876: Supplementary capacities in pixels having special driving circuits and electrodes instead of being connected to common electrode or ground; Use of additional capacitively coupled compensation electrodes - G09G 2310/0262: The addressing of the pixel, in a display other than an active matrix LCD, involving the control of two or more scan electrodes or two or more data electrodes, e.g. pixel voltage dependent on signals of two data electrodes - G09G 2320/103: Detection of image changes, e.g. determination of an index representative of the image change - G09G 2330/021: Power management, e.g. power saving - G09G 2340/0435: Change or adaptation of the frame rate of the video stream - G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00) ## Abstract A display panel of an OLED display device includes a first pixel configured to emit first color light, a second pixel configured to emit second color light, and a third pixel configured to emit third color light. Each of the first, second and third pixels includes at least two transistors, at least one capacitor and an organic light emitting diode. At least one of at least two transistors or at least one capacitor included in the third pixel has a size different from a size of a corresponding one at least two transistors or at least one capacitor included in the first pixel or the second pixel. ## Claims ### Claim 1 A display panel of an organic light emitting diode (OLED) display device, the display panel comprising: a first pixel configured to emit first color light; a second pixel configured to emit second color light; and a third pixel configured to emit third color light, wherein each of the first, second and third pixels includes at least two transistors, at least one capacitor and an organic light emitting diode, and wherein at least one of at least two transistors or at least one capacitor included in the third pixel has a size different from a size of a corresponding one of at least two transistors or at least one capacitor included in the first pixel or the second pixel. ### Claim 2 (depends on 1) The display panel of claim 1, wherein the size of the at least one of the at least two transistors or the at least one capacitor included in the third pixel is determined such that a data voltage range for the third pixel is adjusted close to a data voltage range for the first pixel or the second pixel. ### Claim 3 (depends on 1) The display panel of claim 1, wherein the at least one of the at least two transistors is implemented with a p-type metal-oxide-semiconductor (PMOS) transistor, and another one of the at least two transistors is implemented with an n-type metal-oxide-semiconductor (NMOS) transistor. ### Claim 4 (depends on 1) The display panel of claim 1, wherein the first pixel is a red pixel that emits red light, wherein the second pixel is a green pixel that emits green light, and wherein the third pixel is a blue pixel that emits blue light. ### Claim 5 (depends on 4) The display panel of claim 4, wherein each of the red, green and blue pixels includes: a storage capacitor including a first electrode coupled to a first power supply voltage line and a second electrode coupled to a gate node; a boost capacitor including a first electrode coupled to the gate node, and a second electrode coupled to a gate writing signal line; a first transistor including a gate electrode coupled to the gate node; a second transistor configured to transfer a data voltage to a source of the first transistor in response to a gate writing signal of the gate writing signal line; a third transistor configured to diode-connect the first transistor in response to a gate compensation signal of a gate compensation signal line; a fourth transistor configured to apply an initialization voltage to the gate node in response to a gate initialization signal; a fifth transistor configured to couple the first power supply voltage line and the source of the first transistor in response to an emission signal; a sixth transistor configured to couple a drain of the first transistor and an anode of the organic light emitting diode in response to the emission signal; and a seventh transistor configured to apply an anode initialization voltage to the anode of the organic light emitting diode in response to the gate compensation signal, and wherein the organic light emitting diode includes the anode and a cathode coupled to a second power supply voltage line. ### Claim 6 (depends on 5) The display panel of claim 5, wherein the boost capacitor included in the blue pixel has a capacitance lower than a capacitance of the boost capacitor included in the red pixel or the green pixel. ### Claim 7 (depends on 5) The display panel of claim 5, wherein each of the red, green and blue pixels further includes a parasitic capacitor, and wherein the parasitic capacitor included in the blue pixel has a size different from a size of the parasitic capacitor included in the red pixel or the green pixel. ### Claim 8 (depends on 5) The display panel of claim 5, wherein each of the red, green and blue pixels further includes a negative parasitic boost capacitor between the gate compensation signal line and the gate electrode of the first transistor, and wherein the negative parasitic boost capacitor included in the blue pixel has a capacitance higher than a capacitance of the negative parasitic boost capacitor included in the red pixel or the green pixel. ### Claim 9 (depends on 8) The display panel of claim 8, wherein a width of the gate compensation signal line in the blue pixel is greater than a width of the gate compensation signal line in the red pixel or the green pixel. ### Claim 10 (depends on 8) The display panel of claim 8, wherein an area of the gate electrode of the first transistor in the blue pixel is greater than an area of the gate electrode of the first transistor in the red pixel or the green pixel. ### Claim 11 (depends on 5) The display panel of claim 5, wherein a ratio of a channel width to a channel length of the first transistor in the blue pixel is greater than a ratio of a channel width to a channel length of the first transistor in the red pixel or the green pixel. ### Claim 12 (depends on 11) The display panel of claim 11, wherein the channel width of the first transistor in the blue pixel is greater than the channel width of the first transistor in the red pixel or the green pixel. ### Claim 13 (depends on 11) The display panel of claim 11, wherein the channel length of the first transistor in the blue pixel is less than the channel length of the first transistor in the red pixel or the green pixel. ### Claim 14 (depends on 5) The display panel of claim 5, wherein the storage capacitor included in the blue pixel has a capacitance higher than a capacitance of the storage capacitor included in the red pixel or the green pixel. ### Claim 15 (depends on 5) The display panel of claim 5, wherein the first, second, fifth and sixth transistors are implemented with PMOS transistors, and the third and fourth transistors are implemented with NMOS transistors. ### Claim 16 (depends on 15) The display panel of claim 15, wherein the seventh transistor is implemented with a PMOS transistor. ### Claim 17 (depends on 15) The display panel of claim 15, wherein the seventh transistor is implemented with an NMOS transistor. ### Claim 18 (depends on 4) The display panel of claim 4, wherein each of the red, green and blue pixels includes: a storage capacitor including a first electrode coupled to a first power supply voltage line and a second electrode coupled to a gate node; a first transistor including a gate electrode coupled to the gate node; a second transistor configured to transfer a data voltage to a source of the first transistor in response to a gate writing signal of a gate writing signal line; a third transistor configured to diode-connect the first transistor in response to a gate compensation signal of a gate compensation signal line; a fourth transistor configured to apply an initialization voltage to the gate node in response to a gate initialization signal; a fifth transistor configured to couple the first power supply voltage line and the source of the first transistor in response to an emission signal; a sixth transistor configured to couple a drain of the first transistor and an anode of the organic light emitting diode in response to the emission signal; and a seventh transistor configured to apply an anode initialization voltage to the anode of the organic light emitting diode in response to the gate compensation signal, and wherein the organic light emitting diode includes the anode, and a cathode coupled to a second power supply voltage line. ### Claim 19 (depends on 18) The display panel of claim 18, wherein each of the red, green and blue pixels further includes: a parasitic boost capacitor between the gate writing signal line and the gate electrode of the first transistor; and a negative parasitic boost capacitor between the gate compensation signal line and the gate electrode of the first transistor, and wherein at least one of the parasitic boost capacitor, the negative parasitic boost capacitor, the first transistor and the storage capacitor included in the blue pixel has a size different from a size of a corresponding one of the parasitic boost capacitor, the negative parasitic boost capacitor, the first transistor and the storage capacitor included in the red pixel or the green pixel. ### Claim 20 (depends on 4) The display panel of claim 4, wherein each of the red, green and blue pixels includes: a storage capacitor including a first electrode coupled to a first power supply voltage line, and a second electrode coupled to a gate node; a first transistor including a gate electrode coupled to the gate node; a second transistor configured to transfer a data voltage to a source of the first transistor in response to a gate writing signal of a gate writing signal line; a third transistor configured to diode-connect the first transistor in response to a gate compensation signal of a gate compensation signal line; a fourth transistor configured to apply an initialization voltage to the gate node in response to a gate initialization signal; a fifth transistor configured to couple the first power supply voltage line and the source of the first transistor in response to an emission signal having a low level; a sixth transistor configured to couple a drain of the first transistor and an anode of the organic light emitting diode in response to the emission signal having the low level; and a seventh transistor configured to apply an anode initialization voltage to the anode of the organic light emitting diode in response to the emission signal having a high level, and wherein the organic light emitting diode includes the anode, and a cathode coupled to a second power supply voltage line. ### Claim 21 (depends on 4) The display panel of claim 4, wherein each of the red, green and blue pixels includes: a storage capacitor including a first electrode coupled to a first power supply voltage line, and a second electrode coupled to a gate node; a first transistor including a gate electrode coupled to the gate node; a second transistor configured to transfer a data voltage to a source of the first transistor in response to a gate writing signal of a gate writing signal line; a third transistor configured to diode-connect the first transistor in response to a gate compensation signal of a gate compensation signal line; a fourth transistor configured to apply an initialization voltage to the gate node in response to a gate initialization signal; a fifth transistor configured to couple the first power supply voltage line and the source of the first transistor in response to an emission signal; a sixth transistor configured to couple a drain of the first transistor and an anode of the organic light emitting diode in response to the emission signal; and a seventh transistor configured to apply an anode initialization voltage to the anode of the organic light emitting diode in response to the gate writing signal for a next pixel row, and wherein the organic light emitting diode includes the anode, and a cathode coupled to a second power supply voltage line. ### Claim 22 (depends on 21) The display panel of claim 21, wherein the first, second, fifth and sixth transistors are implemented with PMOS transistors, and the third and fourth transistors are implemented with NMOS transistors. ### Claim 23 (depends on 22) The display panel of claim 22, wherein the seventh transistor is implemented with a PMOS transistor. ### Claim 24 (depends on 22) The display panel of claim 22, wherein the seventh transistor is implemented with an NMOS transistor. ### Claim 25 An organic light emitting diode (OLED) display device comprising: a display panel including a first pixel configured to emit first color light, a second pixel configured to emit second color light, and a third pixel configured to emit third color light; a data driver configured to provide data voltages to the first, second and third pixels; a scan driver configured to provide a gate writing signal, a gate compensation signal and a gate initialization signal to the first, second and third pixels; an emission driver configured to provide an emission signal to the first, second and third pixels; and a controller configured to control the data driver, the scan driver and the emission driver, wherein each of the first, second and third pixels includes at least two transistors, at least one capacitor and an organic light emitting diode, and wherein at least one of at least two transistors or at least one capacitor included in the third pixel has a size different from a size of a corresponding one of at least two transistors or at least one capacitor included in the first pixel or the second pixel.