# US 2022/0044618 A1 · Channel circuit of source driver > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2022/0044618 A1 - Document ID: US20220044618A1 - Status: Published application - Kind: A1 - Application number: 17/506,662 - Filed: 2021-10-20 - Published: 2022-02-10 - Earliest claimed: 2018-07-22 - Assignees: Novatek Microelectronics Corp. - Applicants: Novatek Microelectronics Corp. - Inventors: Yen-Cheng Cheng; Hsiu-Hui Yang - Web page: https://patentgrep.com/patent/US20220044618A1 ## CPC - G09G 3/20: for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix {no fixed position being assigned to or needed to be assigned to the individual characters or partial characters} - G09G 3/2074: {using sub-pixels} - G09G 2310/027: Details of drivers for data electrodes, the drivers handling digital grey scale data, e.g. use of D/A converters - G09G 2310/0291: Details of output amplifiers or buffers arranged for use in a driving circuit - G09G 2310/0297: Special arrangements with multiplexing or demultiplexing of display data in the drivers for data electrodes, in a pre-processing circuitry delivering display data to said drivers or in the matrix panel, e.g. multiplexing plural data signals to one D/A converter or demultiplexing the D/A converter output to multiple columns - G09G 2320/0276: for the purpose of adaptation to the characteristics of a display device, i.e. gamma correction - G09G 2320/0673: for control of gamma adjustment, e.g. selecting another gamma curve - G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00) ## Abstract A source driver, including a plurality of channel circuits, each of the plurality of channel circuits including a first digital-to-analog converter (DAC), a second DAC, a first switch, a second switch and an output buffer circuit, is provided. The output terminal of the output buffer circuit is configured to be coupled to a data line of a display panel. An output terminal of the first DAC is coupled to a first input terminal among the input terminals of the output buffer circuit. An output terminal of the second DAC is coupled to a second input terminal among the input terminals of the output buffer circuit. The first switch is disposed along a first signal path between the output terminal of the first DAC and the output terminal of the output buffer circuit. The second switch is disposed along a second signal path between the output terminal of the second DAC and the output terminal of the output buffer circuit. ## Claims ### Claim 1 A source driver, comprising: a plurality of channel circuits, each of the channel circuits comprising: an output buffer circuit, having a first input terminal, a second input terminal and an output terminal, wherein the output terminal of the output buffer circuit is configured to output a driving voltage according to a gamma voltage to a data line of a display panel in a scan line period; a first digital-to-analog converter and a second digital-to-analog converter, wherein an output terminal of the first digital-to-analog converter is coupled to the first input terminal of the output buffer circuit, and an output terminal of the second digital-to-analog converter is coupled to the second input terminal of the output buffer circuit; a first switch, disposed along a first signal path between the output terminal of the first digital-to-analog converter and the output terminal of the output buffer circuit; and a second switch, disposed along a second signal path between the output terminal of the second digital-to-analog converter and the output terminal of the output buffer circuit, wherein a first output voltage range of the first digital-to-analog converter is different from a second output voltage range of the second digital-to-analog converter. ### Claim 2 (depends on 1) The source driver according to claim 1, wherein: a value range of pixel data is divided into a plurality of sub-ranges, wherein the sub-ranges comprise a first sub-range and a second sub-range; and the first output voltage range is related to the first sub-range, and the second output voltage range is related to the second sub-range. ### Claim 3 (depends on 2) The source driver according to claim 2, further comprising a gamma circuit configured to provide a first gamma voltage having a first level range and a second gamma voltage having a second level range respectively to the first digital-to-analog converter and the second digital-to-analog converter, wherein the first level range is different from the second level range. ### Claim 4 (depends on 2) The source driver according to claim 2, wherein the first sub-range and the second sub-range are a high range and a lower range of the value range of the pixel data, respectively. ### Claim 5 (depends on 2) The source driver according to claim 2, wherein the first sub-range and the second sub-range are not overlapped with each other. ### Claim 6 (depends on 2) The source driver according to claim 2, wherein when a value of pixel data falls within the first sub-range, the first digital-to-analog converter operates to convert the pixel data, and when the value of pixel data does not fall within the first sub-range, the first digital-to-analog converter is idle; and when the value of pixel data falls within the second sub-range, the second digital-to-analog converter operates to convert the pixel data, and when the value of pixel data does not fall within the second sub-range, the second digital-to-analog converter is idle. ### Claim 7 (depends on 1) The source driver according to claim 1, wherein for each value of pixel data, one of the first digital-to-analog converter and the second digital-to-analog converter operates to convert the pixel data, and the other one of the first digital-to-analog converter and the second digital-to-analog converter is idle. ### Claim 8 (depends on 1) The source driver according to claim 1, each of the channel circuits further comprising: a first data latch circuit and a second data latch circuit, an output terminal of the first data latch circuit is coupled to an input terminal of the first digital-to-analog converter, and an output terminal of the second data latch circuit is coupled to an input terminal of the second digital-to-analog converter, and wherein the first data latch circuit is configured to load data according to at least one bit of the pixel data and a loading signal, and the second data latch circuit is configured to load data according to at least one bit of the pixel data and the loading signal. ### Claim 9 (depends on 8) The source driver according to claim 8, wherein a time length of a loading period for the loading signal is equal to a time length of a line latching period for each of the first data latch circuit and the second data latch circuit. ### Claim 10 (depends on 8) The source driver according to claim 8, wherein a first switching timing for the first switch depends upon the at least one bit of the pixel data and a second switching timing for the second switch depends upon depends upon the at least one bit of the pixel data. ### Claim 11 (depends on 1) The source driver according to claim 1, wherein for each value of the pixel data, which one of the first digital-to-analog converter and the second digital-to-analog converter converts the pixel data depends upon the value of the pixel data. ### Claim 12 (depends on 1) The source driver according to claim 1, each of the channel circuits further comprising a first data latch circuit and a second data latch circuit, an output terminal of the first data latch circuit is coupled to an input terminal of the first digital-to-analog converter, and an output terminal of the second data latch circuit is coupled to an input terminal of the second digital-to-analog converter, and wherein the first data latch circuit is configured to load data according to a first loading timing depending upon a first switching timing of the first switch, and the second data latch circuit is configured to load data according to a second loading timing depending upon a second switching timing of the second switch. ### Claim 13 (depends on 12) The source driver according to claim 12, wherein each of the first loading timing and the second loading timing depends upon a location of the pixel data in a frame. ### Claim 14 (depends on 12) The source driver according to claim 12, wherein each of the first loading timing and the second loading timing depends upon at least one bit of the pixel data. ### Claim 15 (depends on 1) The source driver according to claim 1, wherein the output buffer circuit comprises: a first input stage circuit, having an input terminal and an output terminal, wherein the input terminal of the first input stage circuit is employed as or coupled to the first input terminal of the output buffer circuit, and a first terminal of the first switch is coupled to the output terminal of the first input stage circuit; a second input stage circuit, having an input terminal and an output terminal, wherein the input terminal of second input stage circuit is employed as or coupled to the second input terminal of the output buffer circuit, and a first terminal of the second switch is coupled to the output terminal of the second input stage circuit; and a gain and output stage circuit, having an input terminal and an output terminal, wherein the input terminal of the gain and output stage circuit is coupled to a second terminal of the first switch and a second terminal of the second switch, and the output terminal of the gain and output stage circuit is employed as or coupled to the output terminal of the output buffer circuit. ### Claim 16 (depends on 2) The source driver according to claim 2, each of the channel circuits further comprising: a first data latch circuit and a second data latch circuit, wherein an input terminal of each of the first data latch circuit and the second data latch circuit is configured to receive bit data of pixel data, an output terminal of the first data latch circuit is coupled to an input terminal of the first digital-to-analog converter, and an output terminal of the second data latch circuit is coupled to an input terminal of the second digital-to-analog converter. ### Claim 17 (depends on 16) The source driver according to claim 16, wherein: during a first period, the output buffer circuit selects to output a first driving signal related to a signal of the first input terminal of the output buffer circuit via the output terminal of the output buffer circuit, and the second data latch circuit latches and outputs the bit data of the pixel data to the input terminal of the second digital-to-analog converter; and during a second period, the first data latch circuit latches and outputs the bit data of the pixel data to the input terminal of the first digital-to-analog converter, and the output buffer circuit selects to output a second driving signal related to a signal of the second input terminal of the output buffer circuit via the output terminal of the output buffer circuit. ### Claim 18 (depends on 16) The source driver according to claim 16, wherein the first data latch circuit comprises: a first latch, having an input terminal, an output terminal and a control terminal, wherein the input terminal of the first latch is configured to receive the bit data of the pixel data, and the control terminal of the first latch is controlled by a first loading signal; and a first level shifter, having an input terminal and an output terminal, wherein the input terminal of the first level shifter is coupled to the output terminal of the first latch, and the output terminal of the first level shifter is coupled to the input terminal of the first digital-to-analog converter. ### Claim 19 (depends on 18) The source driver according to claim 18, wherein the second data latch circuit comprises: a second latch, having an input terminal, an output terminal and a control terminal, wherein the input terminal of the second latch is configured to receive the bit data of the pixel data, and the control terminal of the second latch is controlled by a second loading signal; and a second level shifter, having an input terminal and an output terminal, wherein the input terminal of the second level shifter is coupled to the output terminal of the second latch, and the output terminal of the second level shifter is coupled to the input terminal of the second digital-to-analog converter. ### Claim 20 (depends on 16) The source driver according to claim 16, wherein when the pixel data belongs to the first sub-range, the first data latch circuit latches and outputs the bit data of the pixel data to the input terminal of the first digital-to-analog converter, and the output buffer circuit selects to output a first driving signal related to a signal of the first input terminal of the output buffer circuit via the output terminal of the output buffer circuit; and when the pixel data belongs to the second sub-range, the second data latch circuit latches and outputs the bit data of the pixel data to the input terminal of the second digital-to-analog converter, and the output buffer circuit selects to output a second driving signal related to a signal of the second input terminal of the output buffer circuit via the output terminal of the output buffer circuit. ### Claim 21 (depends on 16) The source driver according to claim 16, wherein the first data latch circuit comprises: a first latch, having an input terminal and an output terminal, wherein the input terminal of the first latch is configured to receive the bit data of the pixel data, and when the pixel data belongs to the first sub-range and a loading signal is enabled, the first latch latches and outputs the bit data of the pixel data; and a first level shifter, having an input terminal and an output terminal, wherein the input terminal of the first level shifter is coupled to the output terminal of the first latch, and the output terminal of the first level shifter is coupled to the input terminal of the first digital-to-analog converter. ### Claim 22 (depends on 21) The source driver according to claim 21, wherein the second data latch circuit comprises: a second latch, having an input terminal and an output terminal, wherein the input terminal of the second latch is configured to receive the bit data of the pixel data, and when the pixel data belongs to the second sub-range and the loading signal is enabled, the second latch latches and outputs the bit data of the pixel data; and a second level shifter, having an input terminal and an output terminal, wherein the input terminal of the second level shifter is coupled to the output terminal of the second latch, and the output terminal of the second level shifter is coupled to the input terminal of the second digital-to-analog converter. ### Claim 23 (depends on 17) The source driver according to claim 17, wherein: the first data latch circuit and the second data latch circuit receive the bit data of the pixel data from a level shifter; when the pixel data belongs to the first sub-range, the first data latch circuit latches and outputs the bit data of the pixel data to the input terminal of the first digital-to-analog converter; and when the pixel data belongs to the second sub-range, the second data latch circuit latches and outputs the bit data of the pixel data to the input terminal of the second digital-to-analog converter. ### Claim 24 A source driver, comprising: a plurality of channel circuits, each of the channel circuits comprising: an output buffer circuit, at least having a plurality of input terminals and an output terminal, wherein the output terminal of the output buffer circuit is configured to be coupled to a data line of a display panel; a plurality of digital-to-analog converters, comprising a first digital-to-analog converter and a second digital-to-analog converter, wherein an output terminal of the first digital-to-analog converter is coupled to a first input terminal among the input terminals of the output buffer circuit, and an output terminal of the second digital-to-analog converter is coupled to a second input terminal among the input terminals of the output buffer circuit; wherein for each value of the pixel data, one of the first digital-to-analog converter and the second digital-to-analog converts the pixel data and the other one of the first digital-to-analog converter and the second digital-to-analog is idle, and which one of the first digital-to-analog converter and the second digital-to-analog converts the pixel data depends upon the value of the pixel data.