# US 2022/0044099 A1 · Method for in-memory convolutional computation and corresponding integrated circuit > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2022/0044099 A1 - Document ID: US20220044099A1 - Status: Published application - Kind: A1 - Application number: 17/393,075 - Filed: 2021-08-03 - Published: 2022-02-10 - Earliest claimed: 2020-08-06 - Assignees: STMicroelectronics S.r.I.; STMicroelectronics (Rousset) SAS - Applicants: STMicroelectronics S.r.I.; STMicroelectronics (Rousset) SAS - Inventors: Antonino Conte; Francesco La Rosa - Web page: https://patentgrep.com/patent/US20220044099A1 ## CPC - G06N 3/045: Combinations of networks - G11C 11/54: using elements simulating biological cells, e.g. neuron - G06N 3/0464: Convolutional networks [CNN, ConvNet] - G06N 3/065: Analogue means - G11C 13/0004: {comprising amorphous/crystalline phase transition cells} - H10B 63/32: {of the bipolar type} - G11C 13/004: {Reading or sensing circuits or methods} - G11C 13/0069: {Writing or programming circuits or methods} - G11C 2013/0045: {Read using current through the cell} - G11C 2013/0078: {Write using current through the cell} - G06N: COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS - G11C: STATIC STORES (semiconductor memory devices H10B) - H10B: ELECTRONIC MEMORY DEVICES ## Abstract In an embodiment a method for convolutional computation (CNVL) of input values with weight factors includes converting the input values to voltage signals and successively applying the voltage signals on selected bit lines in an array of non-volatile memory points over respective time slots, each memory point comprising a phase-change resistive memory cell coupled to a bit line and having a resistive state corresponding to a weight factor, and a bipolar selection transistor coupled in series with the phase-change resistive memory cell and having a base terminal coupled with a word line, wherein the respective voltage signals bias the respective phase-change memory cells, integrating over the successive time slots read currents resulting from the voltage signals biasing the respective phase-change resistive memory cells and flowing through selected word lines and converting the integrated read currents to output values. ## Claims ### Claim 1 A method for convolutional computation (CNVL) of input values with weight factors, the method comprising: converting the input values to voltage signals and successively applying the voltage signals on selected bit lines in an array of non-volatile memory points over respective time slots, each memory point comprising a phase-change resistive memory cell coupled to a bit line and having a resistive state corresponding to a weight factor, and a bipolar selection transistor coupled in series with the phase-change resistive memory cell and having a base terminal coupled with a word line, wherein the respective voltage signals bias the respective phase-change memory cells; integrating over the successive time slots read currents resulting from the voltage signals biasing the respective phase-change resistive memory cells and flowing through selected word lines; and converting the integrated read currents to output values. ### Claim 2 (depends on 1) The method according to claim 1, further comprising performing a decoding operation by selecting one selected bit line per input value, and selecting one selected word line per output value. ### Claim 3 (depends on 1) The method according to claim 1, wherein the selection bipolar transistors are provided with a β-gain less than 1. ### Claim 4 (depends on 1) The method according to claim 1, wherein the selection bipolar transistors are grouped in groups of multi-emitter bipolar elements, and wherein each bipolar element comprises a number of emitter regions, a shared base region having two symmetrical base terminals coupled to the same word line, and a shared grounded collector region, each phase-change resistive memory cell being coupled with a respective emitter region. ### Claim 5 (depends on 1) The method according to claim 1, further comprises programming the phase-change resistive memory cells in resistive states corresponding to the respective weight factors. ### Claim 6 (depends on 5) The method according to claim 5, wherein programming the phase-change resistive memory cells comprises, for each resistive state, flowing a write current in only one direction. ### Claim 7 (depends on 1) The method according to claim 1, wherein integrating over the successive time slots the read currents comprises using an amplifier coupled with a feedback loop including a capacitive element and a switching circuit capable of reversing a polarity of the capacitive element in the feedback loop in response to a sign control signal. ### Claim 8 (depends on 1) The method according to claim 1, wherein converting the input values to the voltage signals comprises generating an offset voltage compensating for a threshold voltage of the selection bipolar transistors, in addition to a net converted voltage of each input value. ### Claim 9 (depends on 8) The method according to claim 8, wherein converting the input values to the voltage signals comprises emulating a selection bipolar transistor in a biased condition by an emulated read current, in order to generate the offset voltage under in-situ condition. ### Claim 10 (depends on 1) The method according to claim 1, wherein a time slot calibration operation comprises adjusting a time slots duration, in relation to a reference phase-change resistive memory cell and to a reference output value, compensating for possible temperature and process variations of the conductance of the phase-change resistive memory cells and of a β-gain of the selection bipolar transistors. ### Claim 11 (depends on 10) The method according to claim 10, wherein adjusting the time slots duration comprises emulating an output value resulting from integrating the read current resulting from a reference voltage signal biasing the reference phase-change resistive memory cell during an adjustable time slot, and comprises comparing the emulated output value with the reference output value in order to adjust the time slot duration. ### Claim 12 An integrated circuit for convolutional computation (CNVL) of input values with weight factors, the integrated circuit comprising: an array of non-volatile memory points, each non-volatile memory comprising a phase-change resistive memory cell coupled with a bit line and configured to provide a resistive state corresponding to a weight factor, and a selection bipolar transistor coupled in series with the cell and having a base terminal coupled with a word line; an input converter circuit configured to provide and convert the input values to voltage signals and to successively apply the voltage signals on selected bit lines over respective time slots; and an output converter circuit configured to: integrate over the successive time slots read currents resulting from the voltage signals biasing the respective phase-change resistive memory cells and flowing through selected word lines, and convert the integrated read currents to outputs values. ### Claim 13 (depends on 12) The integrated circuit according to claim 12, further comprising a decoder circuit configured to: select one selected bit line per input value, and select one selected word line per output value. ### Claim 14 (depends on 12) The integrated circuit according to claim 12, wherein each selection bipolar transistors has a β-gain inferior than 1. ### Claim 15 (depends on 12) The integrated circuit according to claim 12, wherein the selection bipolar transistors are grouped into multi-emitter bipolar elements, wherein each multi-emitter bipolar element comprising a number of emitter regions, a shared base region having two symmetrical base terminals coupled to the same word line, and a shared grounded collector region, and wherein each phase-change resistive memory cell is coupled with a respective emitter region. ### Claim 16 (depends on 12) The integrated circuit according to claim 12, wherein the output converter circuit comprises, for each selected word line, an integrator circuit comprising an amplifier coupled with a feedback loop including a capacitive element and a switching circuit capable of reversing a polarity of the capacitive element in the feedback loop in response to a sign control signal. ### Claim 17 (depends on 12) The integrated circuit according to claim 12, wherein the input converter circuit is configured to: generate an offset voltage compensating for a threshold voltage of the selection bipolar transistors, and provide a net converted voltage of each input value. ### Claim 18 (depends on 19) The integrated circuit according to claim 19, wherein the input converter circuit comprises an emulating circuit of a memory point configured to emulate a selection bipolar transistor in a biased condition by an emulated read current, in order to generate an offset voltage under in-situ condition. ### Claim 19 (depends on 12) The integrated circuit according to claim 12, wherein a time slots calibration circuit is configured to adjust a time slots duration, in relation to a reference phase-change resistive memory cell and to a reference output value, in order to compensate for possible temperature and process variations of the conductance of the resistive phase-change memory cells and of a β-gain of the selection bipolar transistors. ### Claim 20 (depends on 19) The integrated circuit according to claim 19, wherein the time slot calibration circuit comprises an emulating circuit of a memory point and an emulating circuit of an output converter circuit, configured to emulate an output value resulting from integrating the read current resulting from a reference voltage signal biasing the reference phase-change resistive memory cell during an adjustable time slot, and comprises a comparator configured to compare the emulated output value with the reference output value in order to control a calibration feedback circuit adjusting the time slot duration.