Controlling carry-save adders in multiplication
AssigneeArm Limited
InventorsTai LI, Jack William Derek ANDREW, Michael Alexander KENNEDY
Life of this patent
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Abstract
A multiplier circuit is provided to multiply a first operand and a second operand. The multiplier circuit includes a carry-save adder network comprising a plurality of carry-save adders to perform partial product additions to reduce a plurality of partial products to a redundant result value that represents a product of the first operand and the second operand. A number of the carry-save adders that is used to generate the redundant result value is controllable and is dependent on a width of at least one of the first operand and the second operand.
Claims18
A multiplier circuit to multiply a first operand and a second operand, the multiplier circuit comprising:
- a carry-save adder network comprising a plurality of carry-save adders to perform partial product additions to reduce a plurality of partial products to a redundant result value that represents a product of the first operand and the second operand, wherein
- a number of the carry-save adders that is used to generate the redundant result value is controllable and is dependent on a width of at least one of the first operand and the second operand.
A method of multiplying a first operand and a second operand, the method comprising:
- performing partial product additions to reduce a plurality of partial products to a redundant result value that represents a product of the first operand and the second operand, wherein
- a number of the partial product additions that is used to generate the redundant result value is controllable and is dependent on a width of at least one of the first operand and the second operand.
A multiplier circuit to multiply a first operand and a second operand, the multiplier circuit comprising:
- means for performing partial product additions to reduce a plurality of partial products to a redundant result value that represents a product of the first operand and the second operand, wherein
- a number of the means for performing partial product additions that is used to generate the redundant result value is controllable and is dependent on a width of at least one of the first operand and the second operand.
Dependencies are inferred from the claim text.