# US 2022/0037589 A1 · Multi-doped data storage structure configured to improve resistive memory cell performance

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- Number: US 2022/0037589 A1
- Document ID: US20220037589A1
- Status: Published application
- Kind: A1
- Application number: 16/940,529
- Filed: 2020-07-28
- Published: 2022-02-03
- Earliest claimed: 2020-07-28
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Bi-Shen Lee; Hai-Dang Trinh; Fa-Shen Jiang; Hsun-Chung Kuang
- Web page: https://patentgrep.com/patent/US20220037589A1

## CPC

- H10B 63/30: {comprising selection components having three or more electrodes, e.g. transistors}
- H10N 70/8265: {on sidewalls of dielectric structures, e.g. mesa-shaped or cup-shaped devices}
- G11C 13/0007: {comprising metal oxide memory material, e.g. perovskites}
- H10N 70/24: {based on migration or redistribution of ionic species, e.g. anions, vacancies}
- H10N 70/826: {adapted for essentially vertical current flow, e.g. sandwich or pillar type devices}
- H10N 70/841: {Electrodes}
- H10N 70/8833: {Binary metal oxides, e.g. TaOx}
- G11C 13/0011: {comprising conductive bridging RAM [CBRAM] or programming metallization cells [PMCs]}
- G11C 13/003: {Cell access}
- G11C 13/0069: {Writing or programming circuits or methods}
- G11C 2013/0083: {Write to perform initialising, forming process, electro forming or conditioning}
- G11C 2213/53: Structure wherein the resistive material being in a transistor, e.g. gate
- G11C 2213/79: Array wherein the access device being a transistor
- H10N 70/023: {by chemical vapor deposition, e.g. MOCVD, ALD}
- H10N 70/026: {by physical vapor deposition, e.g. sputtering}
- H10N 70/063: {by etching of pre-deposited switching material layers, e.g. lithography}
- H10B: ELECTRONIC MEMORY DEVICES
- H10N: ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

Various embodiments of the present disclosure are directed towards a memory device including a data storage structure overlying a substrate. A bottom electrode overlies the substrate and a top electrode overlies the bottom electrode. The data storage structure is disposed between the bottom electrode and the top electrode. The data storage structure comprises a dielectric material doped with a first dopant and a second dopant, where the first dopant is different from the second dopant.

## Claims

### Claim 1

A memory device comprising:
a substrate;
a bottom electrode overlying the substrate;
a top electrode overlying the bottom electrode; and
a data storage structure disposed between the top electrode and the bottom electrode, wherein the data storage structure comprises a dielectric material doped with a first dopant and a second dopant, wherein the first dopant is different from the second dopant.

### Claim 2 (depends on 1)

The memory device of claim 1, wherein the dielectric material further comprises a third dopant different from the first and second dopants.

### Claim 3 (depends on 2)

The memory device of claim 2, wherein the dielectric material comprises aluminum oxide, the first dopant comprises nitrogen, the second dopant comprises tantalum, and the third dopant comprises hafnium.

### Claim 4 (depends on 2)

The memory device of claim 2, wherein the dielectric material comprises a first atomic percentage of the first dopant, a second atomic percentage of the second dopant, and a third atomic percentage of the third dopant, wherein the first atomic percentage is less than the second atomic percentage, and the second atomic percentage is less than the third atomic percentage.

### Claim 5 (depends on 4)

The memory device of claim 4, wherein the first atomic percentage is within a range of about 5 to 10 percent, the second atomic percentage is within a range of about 12 to 18 percent, and the third atomic percentage is within a range of about 15 to 22 percent.

### Claim 6 (depends on 1)

The memory device of claim 1, wherein the data storage structure comprises a data storage layer and a multi-doped data storage layer, wherein the multi-doped data storage layer comprises the dielectric material doped with the first dopant and the second dopant, and wherein the data storage layer comprises an undoped metal oxide.

### Claim 7 (depends on 6)

The memory device of claim 6, wherein the data storage layer is devoid of the first dopant.

### Claim 8 (depends on 1)

The memory device of claim 1, further comprising:
a gate dielectric layer overlying the substrate; and
a pair of source/drain regions disposed in the substrate and on opposing sides of the gate dielectric layer;
wherein the bottom electrode is disposed between the gate dielectric layer and the data storage structure, wherein opposing sidewalls of the gate dielectric layer are aligned with opposing sidewalls of the data storage structure.

### Claim 9 (depends on 1)

The memory device of claim 1, wherein the top electrode comprises the first dopant and/or the second dopant.

### Claim 10

An integrated chip comprising:
a substrate; and
a resistive random access memory (RRAM) cell overlying the substrate, wherein the RRAM cell comprises a top electrode, a bottom electrode, and a data storage structure disposed between the top and bottom electrodes, wherein the data storage structure comprises a first high-κ dielectric material and a plurality of dopants, wherein the plurality of dopants comprises a first dopant, a second dopant, and a third dopant that are respectively different from one another.

### Claim 11

(canceled)

### Claim 12

(canceled)

### Claim 13 (depends on 10)

The integrated chip of claim 10, wherein the data storage structure comprises a data storage layer and a multi-doped data storage layer, wherein the multi-doped data storage layer comprises the first high-κ dielectric material doped with the plurality of dopants, and wherein the data storage layer comprises a second high-κ dielectric material.

### Claim 14 (depends on 13)

The integrated chip of claim 13, wherein a thickness of the multi-doped data storage layer is less than a thickness of the data storage layer.

### Claim 15 (depends on 10)

The integrated chip of claim 10, further comprising:
a capping layer disposed between the top electrode and the data storage structure, wherein the capping layer comprises the first dopant and/or the second dopant.

### Claim 16 (depends on 10)

The integrated chip of claim 10, wherein opposing sidewalls of the top electrode, opposing sidewalls of the data storage structure, and opposing sidewalls of the bottom electrode are respectively aligned.

### Claim at position 17

17-20. (canceled)

### Claim 21 (depends on 6)

The memory device of claim 6, wherein opposing sidewalls of the multi-doped data storage layer, opposing sidewalls of the data storage layer, and opposing sidewalls of the top electrode are respectively aligned.

### Claim 22 (depends on 13)

The integrated chip of claim 13, wherein the multi-doped data storage layer directly contacts the bottom electrode, and wherein the data storage layer directly contacts a top surface of the multi-doped data storage layer.

### Claim 23

An integrated chip comprising:
a bottom electrode overlying a substrate;
a top electrode overlying the bottom electrode;
a data storage layer disposed between the top electrode and the bottom electrode; and
a multi-doped data storage layer disposed between the bottom electrode and the data storage layer, wherein the multi-doped data storage layer comprises a dielectric material doped co-doped with a first dopant and a second dopant.

### Claim 24 (depends on 23)

The integrated chip of claim 23, wherein a thickness of the data storage layer is greater than a thickness of the multi-doped data storage layer.

### Claim 25 (depends on 23)

The integrated chip of claim 23, further comprising:
a capping layer disposed between the data storage layer and the top electrode.

### Claim 26 (depends on 25)

The integrated chip of claim 25, wherein the multi-doped data storage layer directly contacts the bottom electrode, wherein the data storage layer directly contacts the capping layer.