# US 2022/0037528 A1 · Vertically-oriented complementary transistor

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- Number: US 2022/0037528 A1
- Document ID: US20220037528A1
- Status: Published application
- Kind: A1
- Application number: 17/094,904
- Filed: 2020-11-11
- Published: 2022-02-03
- Earliest claimed: 2020-07-30
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Chi-Yi Chuang; Hou-Yu Chen; Kuan-Lun Cheng
- Web page: https://patentgrep.com/patent/US20220037528A1

## CPC

- H10D 30/6211: {having fin-shaped semiconductor bodies integral with the bulk semiconductor substrates}
- H10D 88/00: Three-dimensional [3D] integrated devices
- H10D 30/019: {of FETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 30/0198: {forming source or drain electrodes wherein semiconductor bodies are replaced by dielectric layers and the source or drain electrodes extend through the dielectric layers}
- H10D 30/0243: {using dummy structures having essentially the same shapes as the semiconductor bodies, e.g. to provide stability}
- H10D 30/0245: {by further thinning the channel after patterning the channel, e.g. using sacrificial oxidation on fins}
- H10D 30/501: {FETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 84/0128: {Manufacturing their channels}
- H10D 84/013: {Manufacturing their source or drain regions, e.g. silicided source or drain regions}
- H10D 84/0149: {Manufacturing their interconnections or electrodes, e.g. source or drain electrodes}
- H10D 84/0158: {the components including FinFETs}
- H10D 84/016: {the components including vertical IGFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/8311: {the IGFETs characterised by having different channel structures}
- H10D 84/83138: {the IGFETs characterised by having different shapes or dimensions of their gate conductors}
- H10D 84/832: {comprising IGFETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 88/01: {Manufacture or treatment}
- H10P 14/3211: {Silicon, silicon germanium or germanium}
- H10P 14/3411: {Silicon, silicon germanium or germanium}
- H10P 14/6349: {Deposition of epitaxial materials}
- H10W 20/0234: {comprising etching via holes that stop on pads or on electrodes}
- H10W 20/0245: {comprising use of blind vias during the manufacture}
- H10D 62/121: {oriented parallel to substrates}
- H10W 20/023: {the interconnections being through-semiconductor vias}
- H10W 20/40: Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor device according to the present disclosure includes a first transistor and a second transistor disposed over the first transistor. The first transistor includes a plurality of channel members vertically stacked over one another, and a first source/drain feature adjoining the plurality of channel members. The second transistor includes a fin structure, and a second source/drain feature adjoining the fin structure. The semiconductor device further includes a conductive feature electrically connecting the first source/drain feature and the second source/drain feature.

## Claims

### Claim 1

A semiconductor device, comprising:
a first transistor comprising:
a plurality of channel members vertically stacked over one another, and
a first source/drain feature adjoining the plurality of channel members;
a second transistor disposed over the first transistor, the second transistor comprising:
a fin structure, and
a second source/drain feature adjoining the fin structure; and
a conductive feature electrically connecting the first source/drain feature and the second source/drain feature.

### Claim 2 (depends on 1)

The semiconductor device of claim 1,
wherein the first transistor further comprises a first gate structure that wraps around each of the plurality of channel members,
wherein the second transistor further comprises a second gate structure that wraps over the fin structure,
wherein the first gate structure is in contact with the second gate structure.

### Claim 3 (depends on 1)

The semiconductor device of claim 1,
wherein the plurality of channel members comprise silicon (Si),
wherein the fin structure comprises silicon germanium (SiGe).

### Claim 4 (depends on 1)

The semiconductor device of claim 1,
wherein the plurality of channel members comprise silicon (Si), germanium (Ge), silicon germanium (SiGe), molybdenum disulfide (MoS2), tungsten diselenide (WSe2), or hafnium ditelluride (HfTe2).
wherein the fin structure comprises silicon (Si), germanium (Ge), silicon germanium (SiGe), molybdenum disulfide (MoS2), tungsten diselenide (WSe2), or hafnium ditelluride (HfTe2).

### Claim 5 (depends on 1)

The semiconductor device of claim 1, wherein the conductive feature extends through the second source/drain feature.

### Claim 6 (depends on 5)

The semiconductor device as claimed in claim 5, wherein the conductive feature extends through the first source/drain feature.

### Claim 7 (depends on 1)

The semiconductor device of claim 1,
wherein the first transistor further comprises a first source/drain contact disposed over the first source/drain feature,
wherein the second transistor further comprises a second source/drain contact disposed over the second source/drain feature,
wherein the conductive feature is in direct contact with the first source/drain contact and the second source/drain contact.

### Claim 8 (depends on 1)

The semiconductor device of claim 1,
wherein the first transistor further comprises a third source/drain contact disposed below the first source/drain feature,
wherein the second transistor further comprises a fourth source/drain contact disposed over the second source/drain feature,
wherein the conductive feature is in direct contact with the third source/drain contact and the fourth source/drain contact.

### Claim 9

A semiconductor device, comprising:
a first transistor comprising:
a first source feature and a first drain feature, and
a plurality of channel members vertically stacked over one another and extending between the first source feature and the first drain feature; and
a second transistor disposed over the first transistor, the second transistor comprising:
a second source feature and a second drain feature, and
a fin structure extending between the second source feature and the second drain feature,
wherein the second source feature is directly over the first source feature,
wherein the second drain feature is directly over the first drain feature.

### Claim 10 (depends on 9)

The semiconductor device of claim 9,
wherein the first transistor further comprises a first drain contact disposed over the first drain feature,
wherein the second transistor further comprises a second drain contact disposed over the second drain feature.

### Claim 11 (depends on 10)

The semiconductor device of claim 10,
wherein the first drain feature comprises silicon doped with an n-type dopant
wherein the second drain feature comprises silicon germanium doped with a p-type dopant,
wherein the first drain contact and the second drain contact comprise a metal.

### Claim 12 (depends on 10)

The semiconductor device of claim 10,
wherein the first drain contact overhangs the first drain feature,
wherein the second drain contact overhangs the second drain feature.

### Claim 13 (depends on 10)

The semiconductor device of claim 10, further comprising a first conductive feature electrically coupling the first drain contact and the second drain contact.

### Claim 14 (depends on 13)

The semiconductor device of claim 13, wherein the first conductive feature extends through the second drain feature.

### Claim 15 (depends on 10)

The semiconductor device of claim 10,
wherein the first transistor further comprises a first source contact disposed below the first drain feature,
wherein the second transistor further comprises a second source contact disposed over the second drain feature.

### Claim 16

A method, comprising:
forming a first transistor on a first substrate, wherein the first transistor comprises:
a first source feature and a first drain feature,
a plurality of channel members vertically stacked over one another and extending between the first source feature and the first drain feature, and
a first gate structure wrapping around each of the plurality of channel members;
depositing a first passivation layer over the first transistor;
forming an epitaxial layer over a second substrate;
depositing a second passivation layer over the epitaxial layer;
bonding the second passivation layer to the first passivation layer;
after the bonding, removing the second substrate;
patterning the epitaxial layer to form a fin structure over the plurality of channel members; and
forming a second gate structure to wrap over the fin structure, wherein the second gate structure is in contact with the first gate structure.

### Claim 17 (depends on 16)

The method of claim 16, wherein the epitaxial layer comprises silicon germanium.

### Claim 18 (depends on 16)

The method of claim 16, further comprising:
before the forming of the second gate structure, forming a dummy gate stack over a channel region of the fin structure;
recessing a source region and a drain region of the fin structure to form a source recess and a drain recess, the source region and the drain region sandwiching the channel region;
forming a second source feature in the source region and a second drain feature in the drain recess;
depositing a dielectric layer over the second source feature and the second drain feature; and
removing the dummy gate stack.

### Claim 19 (depends on 18)

The method of claim 18, further comprising:
after the forming of the second gate structure, forming a drain contact opening through the second drain feature and the first drain feature; and
forming a conductive feature in the drain contact opening.

### Claim 20 (depends on 18)

The method of claim 18, further comprising:
after the forming of the second gate structure, depositing a third passivation layer over the second gate structure;
depositing a fourth passivation layer over a third substrate;
bonding the fourth passivation layer to the third passivation layer;
removing the first substrate; and
forming a backside source contact electrically coupled to the first source feature.