# US 2022/0037495 A1 · Semiconductor devices > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2022/0037495 A1 - Document ID: US20220037495A1 - Status: Published application - Kind: A1 - Application number: 17/209,290 - Filed: 2021-03-23 - Published: 2022-02-03 - Earliest claimed: 2020-07-29 - Assignees: Samsung Electronics Co., Ltd. - Applicants: Samsung Electronics Co., Ltd. - Inventors: MYUNG GIL KANG; DONG WON KIM; WOO SEOK PARK; KEUN HWI CHO; SUNG GI HUR - Web page: https://patentgrep.com/patent/US20220037495A1 ## CPC - H10D 30/6735: {having gates fully surrounding the channels, e.g. gate-all-around} - H10D 84/0188: {Manufacturing their isolation regions} - H10D 30/019: {of FETs having stacked nanowire, nanosheet or nanoribbon channels} - H10D 30/501: {FETs having stacked nanowire, nanosheet or nanoribbon channels} - H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)} - H10D 62/118: {Nanostructure semiconductor bodies} - H10D 62/121: {oriented parallel to substrates} - H10D 62/364: {of IGFETs} - H10D 64/513: {within recesses in the substrate, e.g. trench gates, groove gates or buried gates} - H10D 84/0172: {Manufacturing their gate conductors} - H10D 84/038: {using silicon technology, e.g. SiGe} - H10D 84/85: Complementary IGFETs, e.g. CMOS - H10D 84/851: {comprising IGFETs having stacked nanowire, nanosheet or nanoribbon channels} - B82Y 10/00: Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic - H10D 84/0135: {Manufacturing their gate conductors} - H10D 84/0151: {Manufacturing their isolation regions} - H10D 84/0167: {Manufacturing their channels} - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES - B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES ## Abstract Semiconductor devices include a first active pattern including a first lower pattern extending in a first direction and a first sheet pattern spaced apart from the first lower pattern; and a first gate electrode on the first lower pattern, the first gate electrode extending in a second direction different from the first direction and surrounding the first sheet pattern, wherein the first lower pattern includes a first sidewall and a second sidewall opposite to each other, each of the first sidewall of the first lower pattern and the second sidewall of the first lower pattern extends in the first direction, the first gate electrode overlaps the first sidewall of the first lower pattern in the second direction by a first depth, the first gate electrode overlaps the second sidewall of the first lower pattern in the second direction by a second depth, and the first depth is different from the second depth. ## Claims ### Claim 1 A semiconductor device comprising: a first active pattern including a first lower pattern extending in a first direction and a first sheet pattern spaced apart from the first lower pattern; and a first gate electrode on the first lower pattern, the first gate electrode extending in a second direction different from the first direction and surrounding the first sheet pattern, wherein the first lower pattern includes a first sidewall and a second sidewall opposite to each other, each of the first sidewall of the first lower pattern and the second sidewall of the first lower pattern extends in the first direction, the first gate electrode overlaps the first sidewall of the first lower pattern in the second direction by a first depth, the first gate electrode overlaps the second sidewall of the first lower pattern in the second direction by a second depth, and the first depth is different from the second depth. ### Claim 2 (depends on 1) The semiconductor device of claim 1, further comprising: a second active pattern including a second lower pattern spaced apart from the first lower pattern in the second direction and a second sheet pattern spaced apart from the second lower pattern; and a gate isolation structure adjacent a first end of the first gate electrode, the first gate electrode further comprising a second end that is spaced apart from the first end in the second direction, wherein the first gate electrode is on the second lower pattern and surrounds the second sheet pattern. ### Claim 3 (depends on 2) The semiconductor device of claim 2, wherein the first sidewall of the first lower pattern is closer than the second sidewall of the first lower pattern to the gate isolation structure, and the first depth is smaller than the second depth. ### Claim 4 (depends on 2) The semiconductor device of claim 2, further comprising a gate insulating layer on a surface of the first sheet pattern, wherein the gate insulating layer extends along a sidewall of the gate isolation structure. ### Claim 5 (depends on 2) The semiconductor device of claim 2, wherein the second lower pattern includes a third sidewall facing the second sidewall of the first lower pattern and a fourth sidewall opposite to the third sidewall, the first gate electrode overlaps the third sidewall of the second lower pattern in the second direction by a third depth, the first gate electrode overlaps the fourth sidewall of the second lower pattern in the second direction by a fourth depth, and the fourth depth is smaller than the third depth. ### Claim 6 (canceled) ### Claim 7 (depends on 5) The semiconductor device of claim 5, wherein the first depth is different from the fourth depth. ### Claim 8 (depends on 1) The semiconductor device of claim 1, further comprising: a second active pattern including a second lower pattern spaced apart from the first lower pattern in the second direction and a second sheet pattern spaced apart from the second lower pattern; a second gate electrode on the second lower pattern, the second gate electrode extending in the second direction and surrounding the second sheet pattern; and a gate isolation structure between the first gate electrode and the second gate electrode. ### Claim 9 (depends on 8) The semiconductor device of claim 8, wherein the second lower pattern includes a third sidewall facing the second sidewall of the first lower pattern, and a fourth sidewall opposite to the third sidewall, the second gate electrode overlaps the third sidewall of the second lower pattern in the second direction by a third depth, the second gate electrode overlaps the fourth sidewall of the second lower pattern in the second direction by a fourth depth, and the third depth is different from the fourth depth. ### Claim 10 (canceled) ### Claim 11 (canceled) ### Claim 12 (depends on 1) The semiconductor device of claim 1, further comprising a fin liner extending along at least a portion of the first sidewall of the first lower pattern and at least a portion of the second sidewall of the first lower pattern. ### Claim 13 (canceled) ### Claim 14 A semiconductor device comprising: a first active pattern including a first lower pattern extending in a first direction on a substrate and a first sheet pattern spaced apart from the first lower pattern; a second active pattern including a second lower pattern spaced apart from the first lower pattern in a second direction that is different from the first direction and a second sheet pattern spaced apart from the second lower pattern; a first gate electrode on the first lower pattern, the first gate electrode extending in the second direction and surrounding the first sheet pattern; and a second gate electrode on the second lower pattern, the second gate electrode extending in the second direction and surrounding the second sheet pattern, wherein the first lower pattern includes a first sidewall and a second sidewall opposite to each other and a first top surface between the first sidewall and the second sidewall of the first lower pattern, each of the first sidewall of the first lower pattern and the second sidewall of the first lower pattern extends in the first direction, the second lower pattern includes a third sidewall facing the second sidewall of the first lower pattern, a fourth sidewall opposite to the third sidewall, and a second top surface between the third sidewall and the fourth sidewall of the second lower pattern, the first gate electrode comprises a first portion that is adjacent the first sidewall of the first lower pattern and protrudes beyond the first top surface toward the substrate by a first depth, the second gate electrode comprises a fourth portion that is adjacent the fourth sidewall of the second lower pattern and protrudes beyond the second top surface toward the substrate by a fourth depth, and the first depth is different from the fourth depth. ### Claim 15 (depends on 14) The semiconductor device of claim 14, further comprising a gate isolation structure between the first gate electrode and the second gate electrode, wherein the first gate electrode and the second gate electrode are spaced apart from each other in second direction and are colinear with each other, the first gate electrode comprises a second portion that is adjacent the second sidewall of the first lower pattern and protrudes beyond the first top surface toward the substrate by a second depth, and the second gate electrode comprises a third portion that is adjacent the third sidewall of the second lower pattern and protrudes beyond the second top surface toward the substrate by a third depth. ### Claim 16 (canceled) ### Claim 17 (depends on 15) The semiconductor device of claim 15, wherein the first depth is equal to the second depth, and the third depth is different from the fourth depth. ### Claim 18 (depends on 14) The semiconductor device of claim 14, further comprising a gate isolation structure between the first lower pattern and the second lower pattern, wherein the first active pattern further includes a third sheet pattern spaced apart from the first sheet pattern in the first direction on the first lower pattern, the first gate electrode and the second gate electrode are spaced apart in the first direction, a short side of the first gate electrode faces the gate isolation structure, and the second gate electrode continuously extends from on the first lower pattern onto the second lower pattern and surrounds the third sheet pattern. ### Claim 19 (depends on 18) The semiconductor device of claim 18, wherein the first gate electrode comprises a second portion that is adjacent the second sidewall of the first lower pattern and protrudes beyond the first top surface toward the substrate by a second depth, the second gate electrode comprises a second portion that is adjacent the second sidewall of the first lower pattern and protrudes beyond the first top surface toward the substrate by a third depth, and the second depth is smaller than the third depth. ### Claim 20 A semiconductor device comprising: a first cell isolation structure and a second cell isolation structure spaced apart from each other in a first direction; a first lower pattern between the first cell isolation structure and the second cell isolation structure, the first lower pattern extending in a second direction that is different from the first direction; a second lower pattern between the first cell isolation structure and the second cell isolation structure, the second lower pattern being spaced apart from the first lower pattern in the first direction; a first sheet pattern above the first lower pattern, the first sheet pattern being spaced apart from the first lower pattern; a second sheet pattern above the second lower pattern, the second sheet pattern being spaced apart from the second lower pattern; a first gate insulating layer extending on a top surface of the first lower pattern and a surface of the first sheet pattern and extending along a sidewall of the first cell isolation structure; and a first gate electrode on the first gate insulating layer, the first gate electrode surrounding the first sheet pattern, wherein the first lower pattern includes a first sidewall and a second sidewall opposite to each other, each of the first sidewall of the first lower pattern and the second sidewall of the first lower pattern extends in the second direction, the first gate electrode overlaps the first sidewall of the first lower pattern in the first direction by a first depth, the first gate electrode overlaps the second sidewall of the first lower pattern in the first direction by a second depth, and the first depth is different from the second depth. ### Claim 21 (canceled) ### Claim 22 (canceled) ### Claim 23 (depends on 20) The semiconductor device of claim 20, further comprising: a second gate electrode extending in the first direction and surrounding the second sheet pattern; and a gate isolation structure between a short side of the first gate electrode and a short side of the second gate electrode, wherein a width of the first cell isolation structure in the first direction is greater than a width of the gate isolation structure in the first direction. ### Claim 24 (depends on 23) The semiconductor device of claim 23, wherein the second lower pattern includes a third sidewall facing the second sidewall of the first lower pattern and a fourth sidewall opposite the third sidewall, the second gate electrode overlaps the third sidewall of the second lower pattern in the first direction by a third depth, the second gate electrode overlaps the fourth sidewall of the second lower pattern in the first direction by a fourth depth, and the third depth is smaller than the fourth depth. ### Claim 25 (canceled) ### Claim 26 (depends on 20) The semiconductor device of claim 20, wherein the first lower pattern is between the first cell isolation structure and the second lower pattern, and the first sidewall of the first lower pattern faces the first cell isolation structure, and wherein the first depth is smaller than the second depth. ### Claim 27 (depends on 20) The semiconductor device of claim 20, wherein the second lower pattern includes a third sidewall facing the second sidewall of the first lower pattern and a fourth sidewall opposite the third sidewall, the first gate electrode overlaps the third sidewall of the second lower pattern in the first direction by a third depth, the first gate electrode overlaps the fourth sidewall of the second lower pattern in the first direction by a fourth depth, and the third depth is greater than the fourth depth, and the first depth is smaller than the second depth. ### Claim 28 (depends on 14) The semiconductor device of claim 14, wherein the first active pattern and the second active pattern are included in a single standard cell.