# US 2022/0037489 A1 · Semiconductor structure and forming method thereof

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- Number: US 2022/0037489 A1
- Document ID: US20220037489A1
- Status: Published application
- Kind: A1
- Application number: 17/404,271
- Filed: 2021-08-17
- Published: 2022-02-03
- Earliest claimed: 2020-07-29
- Applicants: Changxin Memory Technologies, Inc.
- Inventors: CHEONG SOO KIM; YONG GUN KIM; Xianrui HU; GuangSu SHAO
- Web page: https://patentgrep.com/patent/US20220037489A1

## CPC

- H10D 30/601: {having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs (lightly doped source or drain extensions for TFTs H10D30/6715)}
- H10D 64/516: {the thicknesses being non-uniform}
- H10D 30/021: {of FETs having insulated gates [IGFET]}
- H10D 30/0221: {having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or extended-drain MOSFETs [EDMOS]}
- H10D 30/0223: {having source and drain regions or source and drain extensions self-aligned to sides of the gate}
- H10D 30/0227: {having both lightly-doped source and drain extensions and source and drain regions self-aligned to the sides of the gate, e.g. lightly-doped drain [LDD] MOSFET or double-diffused drain [DDD] MOSFET}
- H10D 30/60: Insulated-gate field-effect transistors [IGFET] (H10D30/40 takes precedence)
- H10D 62/102: {Constructional design considerations for preventing surface leakage or controlling electric field concentration}
- H10D 64/01338: {with a treatment, e.g. annealing, after the formation of the conductor}
- H10D 64/021: {using multiple gate spacer layers, e.g. bilayered sidewall spacers}
- H10D 64/664: {the additional layers comprising a barrier layer between the layer of silicon and an upper metal or metal silicide layer}
- H10D 64/68: characterised by the insulator, e.g. by the gate insulator
- H10D 64/683: {being parallel to the channel plane}
- H10D 64/685: {being perpendicular to the channel plane}
- H10D 64/691: {comprising metallic compounds, e.g. metal oxides or metal silicates (insulators comprising nitrogen H10D64/693)}
- H10D 64/693: {the insulator comprising nitrogen, e.g. nitrides, oxynitrides or nitrogen-doped materials}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A semiconductor structure and a forming method thereof are provided. The forming method includes: providing a semiconductor substrate including a source region and a drain region spaced apart; and forming a gate oxide layer, an interface layer and a gate layer on one side of the semiconductor substrate. The gate oxide layer, the interface layer and the gate layer are all disposed between the source region and the drain region. The interface layer is disposed on one side of the gate oxide layer facing away from the semiconductor substrate. The gate layer is disposed on one side of the interface layer facing away from the gate oxide layer. The area of orthographic projection of the interface layer on the semiconductor substrate is smaller than the area of orthographic projection of the gate oxide layer on the semiconductor substrate.

## Claims

### Claim 1

A forming method of a semiconductor structure, comprising:
providing a semiconductor substrate comprising a source region and a drain region spaced apart; and
forming a gate oxide layer, an interface layer and a gate layer on one side of the semiconductor substrate, wherein the gate oxide layer, the interface layer and the gate layer are all disposed between the source region and the drain region, the interface layer is disposed on one side of the gate oxide layer facing away from the semiconductor substrate, the gate layer is disposed on one side of the interface layer facing away from the gate oxide layer, and an area of orthographic projection of the interface layer on the semiconductor substrate is smaller than an area of orthographic projection of the gate oxide layer on the semiconductor substrate.

### Claim 2 (depends on 1)

The forming method of claim 1, wherein a dielectric constant of the interface layer is greater than that of the gate oxide layer.

### Claim 3 (depends on 1)

The forming method of claim 1, further comprising:
forming a barrier layer on a surface and a side wall of a structure constituted by the interface layer and the gate layer together.

### Claim 4 (depends on 1)

The forming method of claim 1, wherein the forming the gate oxide layer, the interface layer and the gate layer on one side of the semiconductor substrate comprises:
sequentially forming a gate oxide layer, an interface layer and a gate layer on a surface of the semiconductor substrate by adopting an atomic layer deposition process;
etching the gate oxide layer, the interface layer and the gate layer by utilizing photolithographic patterning and etching; and
etching a side wall of the interface layer by adopting an isotropic etching process, to enable a width of the interface layer to be smaller than that of the gate oxide layer.

### Claim 5 (depends on 4)

The forming method of claim 4, wherein the etching the gate oxide layer, the interface layer and the gate layer by utilizing photolithographic patterning and etching comprises:
forming a photoresist layer on one side of the gate layer facing away from the interface layer;
exposing and developing the photoresist layer, to form a developing region within which the surface of the gate layer is exposed;
etching the gate oxide layer, the interface layer and the gate layer in the developing region to form a gate structure; and
removing the photoresist layer.

### Claim 6 (depends on 3)

The forming method of claim 3, further comprising:
forming an isolation layer on one side of the barrier layer facing away from the side wall, wherein one end of the isolation layer is flush with one side of the gate layer facing away from the interface layer, and the other end of the isolation layer is in contact with a surface of the semiconductor substrate.

### Claim 7 (depends on 1)

The forming method of claim 1, wherein the gate layer comprises a first dielectric layer, a second dielectric layer and a gate electrode layer, the second dielectric layer is disposed between the first dielectric layer and the gate electrode layer, the first dielectric layer is disposed on a surface of the interface layer facing away from the gate oxide layer, and a material of the second dielectric layer is titanium nitride.

### Claim 8 (depends on 2)

The forming method of claim 2, wherein the gate layer comprises a first dielectric layer, a second dielectric layer and a gate electrode layer, the second dielectric layer is disposed between the first dielectric layer and the gate electrode layer, the first dielectric layer is disposed on a surface of the interface layer facing away from the gate oxide layer, and a material of the second dielectric layer is titanium nitride.

### Claim 9 (depends on 3)

The forming method of claim 3, wherein the gate layer comprises a first dielectric layer, a second dielectric layer and a gate electrode layer, the second dielectric layer is disposed between the first dielectric layer and the gate electrode layer, the first dielectric layer is disposed on a surface of the interface layer facing away from the gate oxide layer, and a material of the second dielectric layer is titanium nitride.

### Claim 10 (depends on 4)

The forming method of claim 4, wherein the gate layer comprises a first dielectric layer, a second dielectric layer and a gate electrode layer, the second dielectric layer is disposed between the first dielectric layer and the gate electrode layer, the first dielectric layer is disposed on a surface of the interface layer facing away from the gate oxide layer, and a material of the second dielectric layer is titanium nitride.

### Claim 11 (depends on 5)

The forming method of claim 5, wherein the gate layer comprises a first dielectric layer, a second dielectric layer and a gate electrode layer, the second dielectric layer is disposed between the first dielectric layer and the gate electrode layer, the first dielectric layer is disposed on a surface of the interface layer facing away from the gate oxide layer, and a material of the second dielectric layer is titanium nitride.

### Claim 12 (depends on 6)

The forming method of claim 6, wherein the gate layer comprises a first dielectric layer, a second dielectric layer and a gate electrode layer, the second dielectric layer is disposed between the first dielectric layer and the gate electrode layer, the first dielectric layer is disposed on a surface of the interface layer facing away from the gate oxide layer, and a material of the second dielectric layer is titanium nitride.

### Claim 13 (depends on 7)

The forming method of claim 7, wherein the semiconductor substrate further comprises:
a drain epitaxial region adjacent to the drain region, wherein other end of the drain epitaxial region is adjacent to an end portion of the gate oxide layer close to the drain region, and a doping concentration of the drain epitaxial region is smaller than that of the drain region.

### Claim 14 (depends on 13)

The forming method of claim 13, wherein the semiconductor substrate further comprises:
a source epitaxial region, wherein one end of the source epitaxial region is adjacent to the source region, the other end of the source epitaxial region is adjacent to an end portion of the gate oxide layer close to the source region, and a doping concentration of the source epitaxial region is smaller than that of the source region.

### Claim 15 (depends on 1)

A semiconductor structure, manufactured by the forming method of the semiconductor structure of any one of claim 1.