# US 2022/0037488 A1 · Semiconductor device

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- Number: US 2022/0037488 A1
- Document ID: US20220037488A1
- Status: Published application
- Kind: A1
- Application number: 17/375,950
- Filed: 2021-07-14
- Published: 2022-02-03
- Earliest claimed: 2020-07-31
- Assignees: Rohm Co., Ltd.
- Applicants: Rohm Co., Ltd.
- Inventors: Masatsugu Yutani; Yuki Shiraishi
- Web page: https://patentgrep.com/patent/US20220037488A1

## CPC

- H10D 64/516: {the thicknesses being non-uniform}
- H10D 30/0295: {using recessing of the source electrodes}
- H10D 30/0297: {using recessing of the gate electrodes, e.g. to form trench gate electrodes}
- H10D 30/665: {having edge termination structures}
- H10D 30/668: {having trench gate electrodes, e.g. UMOS transistors}
- H10D 62/127: {of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs}
- H10D 64/117: {Recessed field plates, e.g. trench field plates or buried field plates}
- H10D 64/252: {for vertical or pseudo-vertical devices}
- H10D 64/2527: {for vertical devices wherein the source or drain electrodes are recessed in semiconductor bodies}
- H10D 64/513: {within recesses in the substrate, e.g. trench gates, groove gates or buried gates}
- H10D 12/481: {having gate structures on slanted surfaces, on vertical surfaces, or in grooves, e.g. trench gate IGBTs}
- H10W 72/07553: {changes in shapes}
- H10W 72/07554: {changes in dispositions}
- H10W 72/536: {the connected ends being ball-shaped}
- H10W 72/537: {Multiple bond wires having different shapes}
- H10W 72/547: {Dispositions of multiple bond wires}
- H10W 72/5473: {multiple bond wires connected to a common bond pad}
- H10W 72/5475: {multiple bond wires connected to common bond pads at both ends of the wires}
- H10W 72/5522: {comprising gold [Au]}
- H10W 72/5524: {comprising aluminium [Al]}
- H10W 72/5525: {comprising copper [Cu]}
- H10W 72/59: Bond pads specially adapted therefor
- H10W 72/926: {Multiple bond pads having different sizes}
- H10W 72/983: {Reinforcing structures, e.g. collars}
- H10W 74/00: Encapsulations, e.g. protective coatings
- H10W 90/756: {between a chip and a stacked lead frame, conducting package substrate or heat sink}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

The present disclosure provides a semiconductor device. The semiconductor device includes a semiconductor chip having a first main surface including an active region and a peripheral region surrounding the active region; a first trench formed in the active region; a first insulating film formed on an inner surface of the first trench; a first electrode formed in the first trench interfacing the first insulating film, and forming a channel in a portion of the semiconductor chip facing the first insulating film; a second trench formed in the peripheral region and having a width greater a width of the first trench; a second insulating film formed on an inner surface of the second trench; and a second electrode formed in the second trench interfacing the second insulating film and electrically coupled to the first electrode.

## Claims

### Claim 1

A semiconductor device, comprising:
a semiconductor chip having a first main surface including an active region and a peripheral region surrounding the active region;
a first trench formed in the active region;
a first insulating film formed on an inner surface of the first trench;
a first electrode formed in the first trench interfacing the first insulating film, and forming a channel in a portion of the semiconductor chip facing the first insulating film;
a second trench formed in the peripheral region and having a width greater a width of the first trench, wherein the second trench extends along a first direction and a second direction intersecting the first direction, and wherein the second trench has a corner portion curved from the first direction to the second direction;
a second insulating film formed on an inner surface of the second trench; and
a second electrode formed in the second trench interfacing the second insulating film and electrically coupled to the first electrode, wherein
the first insulating film has a first thin portion formed at the bottom of the first trench, the first thin portion being selectively thinner than other portions of the first insulating film, and wherein
the second insulating film has a second thin portion formed at the bottom of the corner portion of the second trench, the second thin portion being thinner than other portions of the second insulating film and thicker than the first thin portion.

### Claim 2 (depends on 1)

The semiconductor device according to claim 1, wherein the first insulating film includes a first thin concave portion selectively recessed at the bottom of the first trench in a direction approaching the inner surface of the first trench, and
the first thin portion is sandwiched between the first thin concave portion and the inner surface of the first trench.

### Claim 3 (depends on 1)

The semiconductor device according to claim 1, wherein the second insulating film includes a second thin concave portion selectively recessed at the bottom of the corner portion of the second trench in a direction approaching the inner surface of the second trench, and wherein the second thin portion is sandwiched between the second thin concave portion and the inner surface of the second trench.

### Claim 4 (depends on 1)

The semiconductor device according to claim 1, further comprising:
a connecting trench straddling between the active region and the peripheral region and connecting the first trench and the second trench; and
a connection electrode formed in the connecting trench and connecting the first electrode to the second electrode.

### Claim 5 (depends on 4)

The semiconductor device according to claim 4, further comprising:
an interlayer insulating film formed on the semiconductor chip and covering the first trench and the second trench;
a surface electrode formed on the interlayer insulating film; and
a contact portion formed in the interlayer insulating film and connecting the surface electrode to the second electrode.

### Claim 6 (depends on 5)

The semiconductor device according to claim 5, wherein the connecting trench comprises:
a first connection trench connected to the second trench at a first connection point; and
a second connection trench connected to the second trench at a second connection point separated from the first connection point, wherein
the contact portion is connected to the second electrode at a portion of the second trench between the first connection portion and the second connection portion.

### Claim 7 (depends on 5)

The semiconductor device according to claim 5, wherein the second electrode includes an embedded electrode and a contact hole, the embedded electrode embedded in the second trench, the contact hole penetrating the interlayer insulating film and reaching an intermediate portion of the second electrode in a depth direction of the second trench, and wherein the contact portion includes a contact plug embedded in the contact hole.

### Claim 8 (depends on 7)

The semiconductor device according to claim 7, further comprising a barrier film formed between the contact plug and an inner surface of the contact hole to prevent contact among the contact plug, the interlayer insulating film and the second electrode.

### Claim 9 (depends on 5)

The semiconductor device according to claim 5, wherein the surface electrode comprises:
a pad electrode portion covering the active region and configured to be electrically coupled to the channel; and
a finger electrode portion formed to surround the pad electrode portion and electrically coupled to the second electrode through the contact portion.

### Claim 10 (depends on 1)

The semiconductor device according to claim 1, further comprising:
a third trench formed separately from and outside the second trench in the peripheral region, the third trench having a width greater than the width of the first trench and less than the width of the second trench;
a third insulating film formed on an inner surface of the third trench; and
a third electrode formed in the third trench interfacing the third insulating film, wherein the third electrode is electrically floating.

### Claim 11 (depends on 1)

The semiconductor device according to claim 1, wherein the first trench has a first width substantially between about 0.17 μm and about 0.22 μm, and the second trench has a second width substantially between about 0.5 μm and about 1.0 μm.

### Claim 12 (depends on 1)

The semiconductor device according to claim 1, wherein the second trench has a depth greater than a depth of the first trench.

### Claim 13 (depends on 1)

The semiconductor device according to claim 1, wherein the second trench includes a plurality of trenches having different widths from each other.

### Claim 14 (depends on 1)

The semiconductor device according to claim 1, wherein an inner surface portion of the second trench in contact with the second thin portion has a different surface orientation from an inner surface portion of the first trench in contact with the first thin portion.

### Claim 15 (depends on 1)

The semiconductor device according to claim 1, further comprising a first conductivity type source region, a second conductivity type body region and a first conductivity type drift region sequentially formed from the first main surface of the semiconductor chip in a depth direction of the first trench, wherein the first electrode includes a gate electrode that forms the channel in the body region.

### Claim 16 (depends on 1)

The semiconductor device according to claim 1, wherein the semiconductor chip includes a silicon chip.