# US 2022/0037484 A1 · Method of manufacturing semiconductor device and associated memory device

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- Number: US 2022/0037484 A1
- Document ID: US20220037484A1
- Status: Published application
- Kind: A1
- Application number: 16/943,858
- Filed: 2020-07-30
- Published: 2022-02-03
- Earliest claimed: 2020-07-30
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company Ltd.
- Inventors: NUO XU; ZHIQIANG WU
- Web page: https://patentgrep.com/patent/US20220037484A1

## CPC

- H10D 64/033: {comprising ferroelectric layers}
- G11C 11/221: {using ferroelectric capacitors}
- G11C 11/223: {using MOS with ferroelectric gate insulating film}
- H10B 51/20: characterised by the three-dimensional [3D] arrangements, e.g. with cells on different height levels
- H10B 51/30: characterised by the memory core region
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/025: {of vertical IGFETs (of VDMOS H10D30/0291; of vertical TFTs H10D30/0318)}
- H10D 30/0415: {of FETs having ferroelectric gate insulators}
- H10D 30/701: {IGFETs having ferroelectric gate insulators, e.g. ferroelectric FETs}
- H10D 64/683: {being parallel to the channel plane}
- H10D 64/685: {being perpendicular to the channel plane}
- G11C 11/2259: {Cell access}
- H10D 30/62: Fin field-effect transistors [FinFET]
- H10D 30/6212: {having fin-shaped semiconductor bodies having non-rectangular cross-sections}
- H10D 64/691: {comprising metallic compounds, e.g. metal oxides or metal silicates (insulators comprising nitrogen H10D64/693)}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H10B: ELECTRONIC MEMORY DEVICES

## Abstract

A method of manufacturing a semiconductor device is disclosed. The method includes providing a substrate including a channel region for conducting current; shaping the substrate to form a protruding plane, a bottom plane and a side plane connected between the protruding plane and the bottom plane for the channel region; forming an oxide layer covering the channel region; forming a ferroelectric material strip, extending in a first direction, on a protruding plane of the oxide layer; and forming a gate strip, extending in a second direction orthogonal with the first direction, on the ferroelectric material strip and a side plane and a bottom plane of the oxide layer.

## Claims

### Claim 1

A method of manufacturing a semiconductor device, comprising:
providing a substrate including a channel region for conducting current;
shaping the substrate to form a protruding plane, a bottom plane and a side plane connected between the protruding plane and the bottom plane for the channel region;
forming an oxide layer covering the channel region;
forming a ferroelectric material strip, extending in a first direction, on a protruding plane of the oxide layer; and
forming a gate strip, extending in a second direction orthogonal with the first direction, on the ferroelectric material strip and a side plane and a bottom plane of the oxide layer.

### Claim 2 (depends on 1)

The method of claim 1, wherein shaping the substrate comprises:
executing a photolithography operation upon the substrate to form the protruding plane, the side plane and the bottom plane.

### Claim 3 (depends on 1)

The method of claim 1, wherein forming the oxide layer covering the channel region comprises:
electroplating the oxide layer on the substrate to cover the protruding plane, the bottom plane and the side plane of the channel region.

### Claim 4 (depends on 1)

The method of claim 1, wherein forming the oxide layer covering the channel region comprises:
executing an atomic layer deposition (ALD), a physical vapor deposition (PVD), a chemical vapor phase deposition (CVD), a low pressure CVD (LPCVD) or an alternatively plasma enhanced CVD (PECVD) to form the oxide layer.

### Claim 5 (depends on 1)

The method of claim 1, wherein forming the ferroelectric material strip, extending in the first direction, on the protruding plane of the oxide layer comprises:
electroplating a ferroelectric material upon the protruding plane of the oxide layer to form the ferroelectric material strip.

### Claim 6 (depends on 1)

The method of claim 1, wherein forming the ferroelectric material strip, extending in the first direction, on the protruding plane of the oxide layer comprises:
executing an atomic layer deposition (ALD), a physical vapor deposition (PVD), a chemical vapor phase deposition (CVD), a low pressure CVD (LPCVD) or an alternatively plasma enhanced CVD (PECVD) to form the ferroelectric material strip.

### Claim 7 (depends on 1)

The method of claim 1, wherein forming the ferroelectric material strip, extending in the first direction, on the protruding plane comprises:
depositing a ferroelectric material layer upon the oxide layer; and
shaping the ferroelectric: material layer to make the side plane and the bottom plane of the oxide layer free from being covered by the ferroelectric material layer.

### Claim 8 (depends on 1)

The method of claim 1, wherein shaping the ferroelectric material layer comprises;
disposing a photomask above a part of the ferroelectric material layer, wherein the part of the ferroelectric material layer is located above the protruding plane; and
executing a photolithography operation upon the ferroelectric material layer to form the ferroelectric material strip.

### Claim 9 (depends on 1)

The method of claim 1, wherein an angle between the side plane and the bottom plane ranges from 70 to 90 degrees.

### Claim 10 (depends on 1)

The method of claim 1, wherein a length of the side plane of the channel region along a direction from the protruding plane to the bottom plane ranges from 15 to 80 nm.

### Claim 11 (depends on 1)

The method of claim 1, wherein a length of the bottom plane of the channel region along the second direction ranges from 15 to 50 nm.

### Claim 12 (depends on 1)

The method of claim 1, wherein a length of the protruding plane of the channel region along the second direction ranges from 15 to 50 nm.

### Claim 13 (depends on 1)

The method of claim 1, wherein a thickness of the protruding plane of the oxide layer ranges from 1 to 6 nm.

### Claim 14 (depends on 1)

The method of claim 1, wherein a thickness of the side plane of the oxide layer ranges from 1 to 6 nm.

### Claim 15 (depends on 1)

The method of claim 1, wherein a thickness of the bottom plane of the oxide layer ranges from 15 to 50 nm.

### Claim 16

A method of manufacturing a semiconductor device, comprising:
providing a substrate;
forming a gate electrode layer on the substrate;
generating a trench on the gate electrode layer, wherein a top surface of the substrate is exposed by the trench;
depositing a ferroelectric material layer on a part of a sidewall of the trench;
depositing an oxide layer around the sidewall of the trench, wherein a part of the oxide layer is surrounded by the ferroelectric material layer; and
filling a channel layer into the trench.

### Claim 17 (depends on 16)

The method of claim 16, wherein cross-sectional area of the channel layer is circular or rectangular.

### Claim 18 (depends on 16)

The method of claim 16, wherein the ferroelectric material layer surrounds 25 to 75% of the oxide layer.

### Claim 19

A memory device, comprising:
a plurality of memory cells connected in series, each memory cell includes a first transistor, a second transistor and a capacitor, wherein the first transistor and the second transistor share a gate terminal, a source terminal and a drain terminal, and the capacitor is connected to the gate terminal; and
a selection transistor connected to one end of the plurality of memory cells in series.

### Claim 20 (depends on 19)

The memory device of claim 19, wherein the first transistor includes a ferroelectric field effect transistor (FeFET), and the capacitor includes a ferroelectric capacitor (FeCAP).