# US 2022/0037482 A1 · Symmetric arrangement of field plates in semiconductor devices

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- Number: US 2022/0037482 A1
- Document ID: US20220037482A1
- Status: Published application
- Kind: A1
- Application number: 16/942,734
- Filed: 2020-07-29
- Published: 2022-02-03
- Earliest claimed: 2020-07-29
- Assignees: GLOBALFOUNDRIES U.S.Inc.
- Applicants: Globalfoundries U.S.Inc.
- Inventors: JOHNATAN AVRAHAM KANTAROVSKY; RAJENDRAN KRISHNASAMY; SIVA P. ADUSUMILLI; STEVEN BENTLEY; MICHAEL JOSEPH ZIERAK; JEONGHYUN HWANG
- Web page: https://patentgrep.com/patent/US20220037482A1

## CPC

- H10D 64/112: {comprising multiple field plate segments}
- H10D 30/015: {of FETs having heterojunction interface channels or heterojunction gate electrodes, e.g. HEMT}
- H10D 30/47: having two-dimensional [2D] charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT]
- H10D 30/475: {having wider bandgap layer formed on top of lower bandgap active layer, e.g. undoped barrier HEMTs such as i-AlGaN/GaN HEMTs}
- H10D 30/658: {having trench gate electrodes}
- H10D 30/668: {having trench gate electrodes, e.g. UMOS transistors}
- H10D 30/6894: {having one gate at least partly in a trench}
- H10D 30/699: {having the gate at least partly formed in a trench}
- H10D 62/8503: {Nitride Group III-V materials, e.g. AlN or GaN}
- H10D 64/256: {for lateral devices wherein the source or drain electrodes are recessed in semiconductor bodies (source or drain electrodes of TFTs H10D30/673)}
- H10D 64/411: {for FETs}
- H10D 64/513: {within recesses in the substrate, e.g. trench gates, groove gates or buried gates}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

The present disclosure relates generally to structures in semiconductor devices and methods of forming the same. More particularly, the present disclosure relates to semiconductor devices having field plates that are arranged symmetrically around a gate. The present disclosure provides a semiconductor device including an active region above a substrate, source and drain electrodes in contact with the active region, a gate above the active region and laterally between the source and drain electrodes, a first field plate between the source electrode and the gate, a second field plate between the drain electrode and the gate, in which the gate is spaced apart laterally and substantially equidistant from the first field plate and the second field plate.

## Claims

### Claim 1

A semiconductor device comprising:
an active region above a substrate;
source and drain electrodes in contact with the active region;
a gate above the active region and laterally between the source and drain electrodes;
a first field plate between the source electrode and the gate;
a second field plate between the drain electrode and the gate; and
wherein the gate is spaced apart laterally and substantially equidistant from the first field plate and the second field plate.

### Claim 2 (depends on 1)

The device of claim 1, wherein the first field plate and the second field plate have upper surfaces that are substantially coplanar with an upper surface of the gate.

### Claim 3 (depends on 2)

The device of claim 2, wherein the first field plate is laterally spaced apart from the source electrode, and the second field plate is laterally spaced apart from the drain electrode.

### Claim 4 (depends on 2)

The device of claim 2, wherein the first field plate and the second field plate are individually biased by a voltage.

### Claim 5 (depends on 2)

The device of claim 2, wherein the first field plate is electrically coupled to the source electrode and the second field plate is electrically coupled to the drain electrode.

### Claim 6 (depends on 2)

The device of claim 2, wherein the first field plate and the second field plate are conductively isolated.

### Claim 7 (depends on 2)

The device of claim 2, wherein the gate comprises field plate extensions that extend laterally from the gate towards the source and drain electrodes.

### Claim 8 (depends on 7)

The device of claim 7, wherein the field plate extensions are structured symmetrically around the gate.

### Claim 9 (depends on 8)

The device of claim 8, wherein the field plate extensions are spaced apart laterally from the first field plate and the second field plate.

### Claim 10 (depends on 9)

The device of claim 9, wherein the field plate extensions have upper surfaces that are substantially coplanar with the upper surfaces of the first field plate and the second field plate.

### Claim 11 (depends on 1)

The device of claim 1, wherein the first field plate and the second field plate are formed in a first dielectric layer, and further comprising:
a second dielectric layer above the first dielectric layer;
a third field plate and a fourth field plate formed in the second dielectric layer, wherein the third field plate and the fourth field plate are positioned symmetrically around the gate.

### Claim 12 (depends on 2)

The device of claim 2, wherein the active region comprises a barrier layer disposed on a channel layer.

### Claim 13 (depends on 12)

The device of claim 12, further comprising a gate dielectric layer above the channel layer, wherein the gate is disposed on the gate dielectric layer and the gate dielectric layer is spaced apart from an upper surface of the channel layer by a distance between zero to a thickness of the barrier layer.

### Claim 14 (depends on 12)

The device of claim 12, wherein the gate is disposed above the channel layer, and a lower surface of the gate is spaced apart from an upper surface of the channel layer by a distance between zero to a thickness of the barrier layer.

### Claim 15 (depends on 12)

The device of claim 12, further comprising a capping layer upon the barrier layer, wherein the gate is disposed on the capping layer.

### Claim 16

A semiconductor device comprising:
an active region above a substrate;
source and drain electrodes in contact with the active region;
a gate above the active region and laterally between the source and drain electrodes;
a first set of field plates between the source electrode and the gate, each field plate in the first set is spaced apart from one another;
a second set of field plates between the drain electrode and the gate, each field plate in the second set is spaced apart from one another;
wherein the gate is spaced apart laterally and substantially equidistant from the first set of field plates and the second set of field plates; and
wherein the field plates in the first set and the field plates in the second set have upper surfaces that are substantially coplanar with an upper surface of the gate.

### Claim 17 (depends on 16)

The device of claim 16, wherein the number of field plates in the first set is identical to the number of field plates in the second set.

### Claim 18 (depends on 17)

The device of claim 17, wherein the field plates in the first set and the field plates in the second set are positioned symmetrically around the gate.

### Claim 19 (depends on 18)

The device of claim 18, wherein the spacing between each field plate in the first set is identical to the spacing between each field plate in the second set.

### Claim 20

A method of forming a semiconductor device comprising:
forming an active region above a substrate;
forming
a gate above the active region, a first field plate, and a second field plate, the gate being spaced apart laterally and substantially equidistant from the first field plate and the second field plate; and
forming source and drain electrodes to contact the active region, the gate being laterally between the source and drain electrodes, wherein the first field plate is between the source electrode and the gate, and the second field plate is between the drain electrode and the gate.