# US 2022/0037481 A1 · Semiconductor Structure and its Fabricating Method

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- Number: US 2022/0037481 A1
- Document ID: US20220037481A1
- Status: Published application
- Kind: A1
- Application number: 17/500,089
- Filed: 2021-10-13
- Published: 2022-02-03
- Earliest claimed: 2020-06-05
- Assignees: Changxin Memory Technologies, Inc.
- Applicants: Changxin Memory Technologies, Inc.
- Inventors: Bing ZOU; Cheng Yeh HSU
- Web page: https://patentgrep.com/patent/US20220037481A1

## CPC

- H10D 64/01: Manufacture or treatment
- H10B 12/485: {Bit line contacts}
- H10B 12/488: {Word lines}
- H10B 99/00: Subject matter not provided for in other groups of this subclass
- H10D 30/60: Insulated-gate field-effect transistors [IGFET] (H10D30/40 takes precedence)
- H10D 64/027: {by etching at gate locations}
- H10D 64/256: {for lateral devices wherein the source or drain electrodes are recessed in semiconductor bodies (source or drain electrodes of TFTs H10D30/673)}
- H10D 64/513: {within recesses in the substrate, e.g. trench gates, groove gates or buried gates}
- H10D 84/0126: {the components including insulated gates, e.g. IGFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10P 30/204: {into Group IV semiconductors}
- H10P 30/21: {of electrically active species}
- H10P 74/203: {Structural properties, e.g. testing or measuring thicknesses, line widths, warpage, bond strengths or physical defects}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10B: ELECTRONIC MEMORY DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

Embodiments of the present application provide a semiconductor structure and its fabricating method, and a semiconductor memory. The method of fabricating a semiconductor structure comprises providing a substrate and performing ion implantation on the substrate to form an active area, forming a gate groove on surface of the substrate, measuring depth of the gate groove, and performing ion implantation compensation, if the depth of the gate groove meets a preset condition, on the substrate according to the depth of the gate groove, and forming an ion compensation region in the active area at one side of the gate groove.

## Claims

### Claim 1

A method of fabricating a semiconductor structure, comprising:
providing a substrate and performing ion implantation on the substrate to form an active area;
forming a gate groove on surface of the substrate;
measuring depth of the gate groove; and
performing ion implantation compensation, if the depth of the gate groove meets a preset condition, on the substrate according to the depth of the gate groove, and forming an ion compensation region in the active area at one side of the gate groove.

### Claim 2 (depends on 1)

The method of fabricating a semiconductor structure according to claim 1, wherein the step of forming an ion compensation region in the active area at one side of the gate groove comprises:
forming a bitline contact hole in the active area at one side of the gate groove; and
performing ion implantation compensation on the substrate through the bitline contact hole, and forming the ion compensation region.

### Claim 3 (depends on 1)

The method of fabricating a semiconductor structure according to claim 1, wherein the step of performing ion implantation compensation on the substrate according to the depth of the gate groove comprises:
fixing implantation depth of compensation ions according to the depth of the gate groove;
fixing implantation energy of the compensation ions according to the implantation depth of the compensation ions; and
performing ion implantation compensation on the substrate, and forming the ion compensation region according to the implantation energy of the compensation ions.

### Claim 4 (depends on 1)

The method of fabricating a semiconductor structure according to claim 1, wherein the preset condition is that the depth of the gate groove is less than a target depth, and that an absolute value of the difference between the depth of the gate groove and the target depth is greater than a threshold standard deviation;
the threshold standard deviation is determined according to a result of statistics about depths of plural gate grooves made with the target depth as a processing parameter.

### Claim 5 (depends on 4)

The method of fabricating a semiconductor structure according to claim 4, wherein the step of fixing the threshold standard deviation comprises measuring depths of a plurality of the gate grooves, calculating an average value of the depths of the plurality of gate grooves, and calculating a standard deviation of the depths of the plurality of gate grooves, wherein the standard deviation is the threshold standard deviation.

### Claim 6 (depends on 2)

The method of fabricating a semiconductor structure according to claim 2, wherein the step of forming a gate groove on surface of the substrate comprises:
forming on surface of the substrate a shallow trench isolation structure separating the active area into plural blocks; and
forming the gate groove on surface of the substrate, depth of the gate groove being less than depth of the shallow trench isolation structure.

### Claim 7 (depends on 6)

The method of fabricating a semiconductor structure according to claim 6, wherein after measuring the depth of the gate groove are further included the following steps:
sequentially forming a gate oxidizing layer and a diffusion barrier layer on surface of the gate groove;
filling a wordline in the gate groove; and
forming a protective layer on surfaces of the wordline and the substrate.

### Claim 8 (depends on 7)

The method of fabricating a semiconductor structure according to claim 7, wherein a method of forming the gate oxidizing layer includes thermal oxidation process or deposition process.

### Claim 9 (depends on 7)

The method of fabricating a semiconductor structure according to claim 7, wherein the step of filling a wordline in the gate groove comprises:
forming a metal layer on surface of the diffusion barrier layer; and
etching back the metal layer, with remaining metal layer serving as the wordline, and an upper surface of the wordline being lower than an upper surface of the substrate.

### Claim 10 (depends on 7)

The method of fabricating a semiconductor structure according to claim 7, wherein the step of forming a bitline contact hole in the active area at one side of the gate groove comprises:
etching the protective layer to form the bitline contact hole; wherein the bitline contact hole penetrates through the protective layer, and exposes the substrate; the bitline contact hole is located between two adjacent ones of the gate grooves in the same and single active area.

### Claim 11

A semiconductor structure, comprising:
a substrate, a gate groove, and an ion compensation region; and
an active area, disposed in the substrate; wherein the ion compensation region is located in the active area at one side of the gate groove whose depth meets a preset condition.

### Claim 12 (depends on 11)

The semiconductor structure according to claim 11, further comprising a bitline contact hole, whose vertical projection onto the substrate at least partially overlaps with vertical projection of the ion compensation region onto the substrate.

### Claim 13 (depends on 12)

The semiconductor structure according to claim 12, further comprising a shallow trench isolation structure, which is located at surface of the substrate and separates the active area into plural blocks; wherein depth of the gate groove is less than depth of the shallow trench isolation structure.

### Claim 14 (depends on 13)

The semiconductor structure according to claim 13, wherein the gate groove is located between two adjacent ones of the shallow trench isolation structures.

### Claim 15 (depends on 13)

The semiconductor structure according to claim 13, further comprising:
a gate oxidizing layer and a diffusion barrier layer disposed on surface of the gate groove;
a wordline disposed in the gate groove; and
a protective layer disposed on surfaces of the wordline and the substrate; wherein the bitline contact hole penetrates through the protective layer and exposes the substrate, and the bitline contact hole is located between two adjacent ones of the gate grooves in the same and single active area.