# US 2022/0037451 A1 · Electronic apparatus > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2022/0037451 A1 - Document ID: US20220037451A1 - Status: Published application - Kind: A1 - Application number: 17/365,966 - Filed: 2021-07-01 - Published: 2022-02-03 - Earliest claimed: 2020-07-31 - Assignees: Samsung Display Co., Ltd. - Applicants: Samsung Display Co., Ltd. - Inventors: WONKYU KWAK; Jinhee Jang; Jae-Sic Lee; Minchae Kwak; Byungsun Kim; Hansol Kim; Changsoo Pyon; Jae Yong Lee; Jae-Ho Choi - Web page: https://patentgrep.com/patent/US20220037451A1 ## CPC - G09G 3/3233: with pixel circuitry controlling the current through the light-emitting element - G09G 3/3266: Details of drivers for scan electrodes - G09G 3/3275: Details of drivers for data electrodes - H10K 59/12: Active-matrix OLED [AMOLED] displays - H10K 59/131: Interconnections, e.g. wiring lines or terminals - H10K 59/873: {Encapsulations} - G09G 2300/0426: Layout of electrodes and connections - G09G 2360/144: the light being ambient light - H10K 59/65: OLEDs integrated with inorganic image sensors - G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00) - H10K: ORGANIC ELECTRIC SOLID-STATE DEVICES ## Abstract An electronic apparatus includes a base substrate having a first region, a second region at least partially surrounded by the first region, and a display region at least partially surrounding the first region, a plurality of pixels disposed on the base substrate, each of which includes a transistor and a light emitting element connected to the transistor, a hole line connecting pixels with the second region interposed therebetween, and a hole pattern electrically insulated from the hole line, disposed in the first region, and at least partially surrounding the second region. ## Claims ### Claim 1 An electronic apparatus, comprising: a base substrate including a first region, a second region at least partially surrounded by the first region, and a display region at least partially surrounding the first region; a plurality of pixels disposed on the base substrate, each of the plurality of pixels including a circuit element layer, including a transistor, and a display element layer, including a light emitting element connected to the transistor; a plurality of hole lines connecting pixels of the plurality of pixels, wherein the second region is interposed between neighboring pixels of the plurality of pixels that are connected to each other by the plurality of hole lines; and a hole pattern electrically insulated from the plurality of hole lines, disposed in the first region, and at least partially surrounding the second region. ### Claim 2 (depends on 1) The electronic apparatus of claim 1, wherein each of the plurality of pixels receives a power voltage and is connected to both a scan line, transmitting a scan signal, and to a data line, transmitting a data signal. ### Claim 3 (depends on 2) The electronic apparatus of claim 2, further comprising a hole pattern control unit receiving the power voltage and provide a hole pattern signal to the hole pattern in response to the scan signal. ### Claim 4 (depends on 3) The electronic apparatus of claim 3, wherein the hole pattern control unit comprises a hole pattern transistor including a first electrode receiving the power voltage, a second electrode outputting the hole pattern signal, and a first gate electrode receiving the scan signal. ### Claim 5 (depends on 3) The electronic apparatus of claim 3, wherein the hole pattern control unit comprises: a first hole pattern transistor including a third electrode receiving the power voltage, a fourth electrode connected to a first node, and a second gate electrode receiving the scan signal; at least one second hole pattern transistor including a fifth electrode connected to the first node, a sixth electrode connected to a second node outputting the hole pattern signal, and a third gate electrode connected to the first node; and at least one third hole pattern transistor including a seventh electrode connected to the second node, a eight electrode connected to the first node, and a fourth gate electrode connected to the second node. ### Claim 6 (depends on 2) The electronic apparatus of claim 2, further comprising a hole pattern control unit receiving the power voltage and provide a hole pattern signal to the hole pattern. ### Claim 7 (depends on 6) The electronic apparatus of claim 6, wherein the hole pattern control unit comprises: a first hole pattern transistor including a first electrode connected to a first node receiving the power voltage, a second electrode connected to a second node outputting the hole pattern signal, and a first gate electrode connected to the first node; and a second hole pattern transistor including a third electrode connected to the second node, a fourth electrode connected to the first node, and a second gate electrode connected to the second node. ### Claim 8 (depends on 2) The electronic apparatus of claim 2, wherein the plurality of hole lines comprise scan hole lines connected to the scan line, and data hole lines that are insulated, spaced apart from the scan hole lines, and connected to the data line, wherein the scan hole lines and the data hole lines are arranged in an alternating pattern. ### Claim 9 (depends on 8) The electronic apparatus of claim 8, wherein: the circuit element layer comprises first to fourth insulation layers sequentially stacked on the base substrate; and the transistor comprises: a semiconductor pattern disposed on the first insulation layer; a control electrode disposed on the second insulation layer and insulated from and at least partially overlapping the semiconductor pattern; an upper electrode disposed on the third insulation layer and insulated from and at least partially overlapping the control electrode; and an input electrode and an output electrode each disposed on the fourth insulation layer and connected to opposing sides of the semiconductor pattern through contact holes defined in each of the first to fourth insulation layers. ### Claim 10 (depends on 9) The electronic apparatus of claim 9, wherein the hole pattern is disposed below the plurality of hole lines, and is disposed on any one layer of the first insulation layer and the second insulation layer. ### Claim 11 (depends on 9) The electronic apparatus of claim 9, wherein: the hole pattern comprises a central portion at least partially surrounding the second region and a protruding portion which protrudes in one direction from an edge of the hole pattern; the scan line comprises a first scan line spaced apart from the protruding portion and a second scan line spaced apart from the first scan line, at least partially overlapping the protruding portion and the central portion, and connected to a corresponding scan hole line among the scan hole lines; and the circuit element layer further comprises a bridge pattern connecting the first scan line and the second scan line. ### Claim 12 (depends on 1) The electronic apparatus of claim 1, further comprising an electronic module at least partially overlapping the second region and disposed below the display region. ### Claim 13 (depends on 1) The electronic apparatus of claim 1, further comprising an encapsulation substrate disposed on the display element layer, and a sealing member spaced apart from an edge of the display region and coupling the circuit element layer and the encapsulation substrate, wherein a gap is formed between the encapsulation substrate and the display element layer. ### Claim 14 (depends on 13) The electronic apparatus of claim 13, wherein the base substrate and the encapsulation substrate are rigid, and pixels of the plurality of pixels are omitted in a region of the base substrate overlapping the second region. ### Claim 15 (depends on 1) The electronic apparatus of claim 1, further comprising a first inorganic layer covering the display element layer, a second inorganic layer disposed on the first inorganic layer, and a thin film encapsulation layer, including an organic layer, disposed between the first inorganic layer and the second inorganic layer. ### Claim 16 (depends on 15) The electronic apparatus of claim 15, wherein the base substrate is flexible, and the electronic apparatus further includes: a module hole penetrating the base substrate, the circuit element layer, the display element layer, and the thin film encapsulation layer, wherein the module hole at least partially overlaps the second region. ### Claim 17 (depends on 1) The electronic apparatus of claim 1, wherein the hole pattern has a circular shape, an elliptical shape, or a polygonal shape. ### Claim 18 (depends on 1) The electronic apparatus of claim 1, wherein the hole pattern comprises division patterns spaced apart from each other. ### Claim 19 An electronic apparatus, comprising: a base substrate including a display region and a non-display region adjacent to the display region, the display region including a first region and a second region at least partially surrounded by the first region and having a higher light transmittance than the first region; a plurality of pixels disposed on the base substrate, each of the plurality of pixels receiving a power voltage, and each connected to a scan line transmitting a scan signal and a data line transmitting a data signal; a plurality of hole lines connecting pixels of the plurality of pixels, wherein the second region is interposed between neighboring pixels of the plurality of pixels that are connected to each other by the plurality of hole lines; and a hole pattern insulted from and at least partially overlapping the plurality of hole lines and at least partially surrounding the second region, wherein the hole pattern is spaced apart from the second region and is closer to the base substrate than the plurality of hole lines is to the base substrate. ### Claim 20 (depends on 19) The electronic apparatus of claim 19, further comprising a hole pattern control unit receiving the power voltage and provide a hole pattern signal to the hole pattern in response to the scan signal. ### Claim 21 (depends on 20) The electronic apparatus of claim 20, wherein the hole pattern control unit comprises: a hole pattern transistor including a first electrode receiving the power voltage; a second electrode outputting the hole pattern signal; and a gate electrode receiving the scan signal. ### Claim 22 (depends on 20) The electronic apparatus of claim 20, wherein the hole pattern control unit comprises: a first hole pattern transistor including a first electrode receiving the power voltage, a second electrode connected to a first node, and a first gate electrode receiving the scan signal; at least one second hole pattern transistor including a second electrode connected to the first node, a third electrode connected to a second node outputting the hole pattern signal, and a second gate electrode connected to the first node; and at least one third hole pattern transistor including a fourth electrode connected to the second node, a fifth electrode connected to the first node, and a third gate electrode connected to the second node. ### Claim 23 (depends on 19) The electronic apparatus of claim 19, further comprising a hole pattern control unit receiving the power voltage and provide a hole pattern signal to the hole pattern. ### Claim 24 (depends on 23) The electronic apparatus of claim 23, wherein the hole pattern control unit comprises: a first hole pattern transistor including a first electrode connected to a first node receiving the power voltage, a second electrode connected to a second node outputting the hole pattern signal, and a first gate electrode connected to the first node; and a second hole pattern transistor including a third electrode connected to the second node, a fourth electrode connected to the first node, and a second gate electrode connected to the second node.