# US 2022/0037441 A1 · Display device

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- Number: US 2022/0037441 A1
- Document ID: US20220037441A1
- Status: Published application
- Kind: A1
- Application number: 17/451,201
- Filed: 2021-10-18
- Published: 2022-02-03
- Earliest claimed: 2019-01-18
- Assignees: Samsung Display Co., Ltd.
- Applicants: Samsung Display Co., Ltd.
- Inventors: JUN HYUN PARK; DONG WOO KIM; SUNG JAE MOON; KANG MOON JO
- Web page: https://patentgrep.com/patent/US20220037441A1

## CPC

- H10D 86/481: {integrated with passive devices, e.g. auxiliary capacitors}
- H10K 59/1216: {the pixel elements being capacitors}
- H10D 86/441: {Interconnections, e.g. scanning lines}
- H10D 86/60: wherein the TFTs are in active matrices
- H10K 59/1213: {the pixel elements being TFTs}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10K: ORGANIC ELECTRIC SOLID-STATE DEVICES

## Abstract

A display device having high resolution includes: a first conductive layer, an active pattern, second to fourth conductive layers, and a pixel electrode sequentially formed on a substrate, with first to fourth insulating layers separately interposed therebetween, the first conductive layer including a lower pattern, the active pattern including a source region, a channel region, and a drain region, the second conductive layer including a gate electrode overlapping the channel region and a driving gate electrode connected to the gate electrode, the third conductive layer including a capacitor electrode overlapping the driving gate electrode, the fourth conductive layer including an additional capacitor electrode overlapping the capacitor electrode. The driving gate electrode and the capacitor electrode may form a storage capacitor, the pixel electrode and the additional capacitor electrode may form a first additional capacitor, and the capacitor electrode and the additional capacitor electrode may form a second additional capacitor.

## Claims

### Claim 1

A display device comprising:
a substrate;
a first conductive layer including a lower pattern disposed on the substrate;
a first insulating layer disposed on the first conductive layer;
an active pattern disposed on the first insulating layer and including a source region, a channel region, and a drain region;
a second conductive layer disposed on the active pattern and including a gate electrode overlapping the channel region and a driving gate electrode connected to the gate electrode;
a second insulating layer disposed on the second conductive layer;
a third conductive layer disposed on the second insulating layer and including a capacitor electrode overlapping the driving gate electrode;
a third insulating layer disposed on the third conductive layer;
a fourth conductive layer disposed on the third insulating layer and including an additional capacitor electrode overlapping the capacitor electrode;
a fourth insulating layer disposed on the fourth conductive layer; and
a pixel electrode layer including a pixel electrode disposed on the fourth insulating layer,
wherein the driving gate electrode and the capacitor electrode form a storage capacitor, the pixel electrode and the additional capacitor electrode form a first additional capacitor, and the capacitor electrode and the additional capacitor electrode form a second additional capacitor.