# US 2022/0037362 A1 · Three-Dimensional Memory Device and Method

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- Number: US 2022/0037362 A1
- Document ID: US20220037362A1
- Status: Published application
- Kind: A1
- Application number: 17/140,888
- Filed: 2021-01-04
- Published: 2022-02-03
- Earliest claimed: 2020-07-30
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Meng-Han Lin; Han-Jong Chia; Sheng-Chen Wang; Feng-Cheng Yang; Yu-Ming Lin; Chung-Te Lin
- Web page: https://patentgrep.com/patent/US20220037362A1

## CPC

- H10B 51/20: characterised by the three-dimensional [3D] arrangements, e.g. with cells on different height levels
- H10D 64/033: {comprising ferroelectric layers}
- H10B 51/00: Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors
- H10B 51/10: characterised by the top-view layout
- H10B 51/30: characterised by the memory core region
- H10D 30/0415: {of FETs having ferroelectric gate insulators}
- H10D 30/701: {IGFETs having ferroelectric gate insulators, e.g. ferroelectric FETs}
- H10D 64/252: {for vertical or pseudo-vertical devices}
- H10D 64/258: {characterised by the relative positions of the source or drain electrodes with respect to the gate electrode}
- H10D 64/689: {having ferroelectric layers}
- H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
- H10B: ELECTRONIC MEMORY DEVICES
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

In an embodiment, a device includes: a word line extending in a first direction; a data storage layer on a sidewall of the word line; a channel layer on a sidewall of the data storage layer; a back gate isolator on a sidewall of the channel layer; and a bit line having a first main region and a first extension region, the first main region contacting the channel layer, the first extension region separated from the channel layer by the back gate isolator, the bit line extending in a second direction, the second direction perpendicular to the first direction.

## Claims

### Claim 1

A device comprising:
a word line extending in a first direction;
a data storage layer on a sidewall of the word line;
a channel layer on a sidewall of the data storage layer;
a back gate isolator on a sidewall of the channel layer; and
a bit line having a first main region and a first extension region, the first main region contacting the channel layer, the first extension region separated from the channel layer by the back gate isolator, the bit line extending in a second direction, the second direction perpendicular to the first direction.

### Claim 2 (depends on 1)

The device of claim 1, wherein the first main region of the bit line is separated from the sidewall of the data storage layer by the channel layer.

### Claim 3 (depends on 1)

The device of claim 1, wherein the first main region of the bit line contacts the sidewall of the data storage layer and a single sidewall of the channel layer.

### Claim 4 (depends on 1)

The device of claim 1, wherein the first main region of the bit line contacts the sidewall of the data storage layer and a plurality of sidewalls of the channel layer.

### Claim 5 (depends on 1)

The device of claim 1 further comprising:
a source line having a second main region and a second extension region, the second main region contacting the channel layer, the second extension region separated from the channel layer by the back gate isolator, the source line extending in the second direction; and
an isolation region between the source line and the bit line.

### Claim 6 (depends on 5)

The device of claim 5, wherein the isolation region, the first extension region of the bit line, and the second extension region of the source line have a same width in a third direction, the third direction perpendicular to the first direction and the second direction.

### Claim 7 (depends on 5)

The device of claim 5, wherein the isolation region has a first width in the first direction and the back gate isolator has a second width in the first direction, the second width greater than the first width.

### Claim 8 (depends on 1)

The device of claim 1, wherein the back gate isolator comprises aluminum oxide.

### Claim 9

A device comprising:
a bit line extending in a first direction, the bit line having a first T-shaped cross-section in a top-down view;
a source line extending in the first direction, the source line having a second T-shaped cross-section in the top-down view;
an isolation region between the source line and the bit line;
a word line extending in a second direction, the second direction perpendicular to the first direction;
a back gate isolator between the word line and each of the isolation region, a first portion of the bit line, and a second portion of the source line;
a channel layer between the back gate isolator and the word line; and
a data storage layer between the channel layer and the word line.

### Claim 10 (depends on 9)

The device of claim 9, wherein the isolation region has a first width in the second direction, and the back gate isolator has a second width in the second direction, the second width greater than the first width.

### Claim 11 (depends on 10)

The device of claim 10, wherein the channel layer has the second width in the second direction.

### Claim 12 (depends on 10)

The device of claim 10, wherein the channel layer has a third width in the second direction, and a combination of the bit line, the source line, and the isolation region has a fourth width in the second direction, the third width greater than the second width and less than the fourth width.

### Claim 13 (depends on 10)

The device of claim 10, wherein the channel layer has a third width in the second direction, and a combination of the bit line, the source line, and the isolation region has the third width in the second direction, the third width greater than the second width.

### Claim 14 (depends on 10)

The device of claim 10 further comprising:
a source line interconnect over and connected to the source line; and
a bit line interconnect over and connected to the bit line.

### Claim 15 (depends on 10)

The device of claim 10, wherein the back gate isolator comprises aluminum oxide.

### Claim 16

A method comprising:
forming a word line between a pair of first dielectric layers;
depositing a data storage layer on sidewalls of the first dielectric layers and a sidewall of the word line;
depositing a channel layer on a sidewall of the data storage layer;
depositing a first dielectric layer on a sidewall of the channel layer;
forming a first isolation region on a sidewall of the first dielectric layer;
removing a first portion of the first isolation region, a second portion of the first isolation region remaining after the removing;
after removing the first portion of the first isolation region, patterning the first dielectric layer to form a back gate isolator; and
forming a bit line and a source line at opposing sides of the second portion of the first isolation region, the back gate isolator separating the channel layer from a first portion of the bit line and a second portion of the source line.

### Claim 17 (depends on 16)

The method of claim 16 further comprising:
patterning the channel layer while patterning the first dielectric layer.

### Claim 18 (depends on 16)

The method of claim 16 further comprising:
forming a second isolation region extending through the channel layer; and
patterning the channel layer while forming the second isolation region.

### Claim 19 (depends on 16)

The method of claim 16 further comprising:
forming a second isolation region extending through the channel layer; and
patterning the channel layer after patterning the first dielectric layer and before forming the second isolation region.

### Claim 20 (depends on 16)

The method of claim 16, wherein the first dielectric layer is formed of aluminum oxide.