# US 2022/0037360 A1 · Device, a Method Used in Forming a Circuit Structure, a Method Used in Forming an Array of Elevationally-Extending Transistors and a Circuit Structure Adjacent Thereto > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2022/0037360 A1 - Document ID: US20220037360A1 - Status: Published application - Kind: A1 - Application number: 17/504,313 - Filed: 2021-10-18 - Published: 2022-02-03 - Earliest claimed: 2017-09-14 - Assignees: Micron Technology, Inc. - Applicants: Micron Technology, Inc. - Inventors: Paolo Tessariol; Justin B. Dorhout; Indra V. Chary; Jun Fang; Matthew Park; Zhiqiang Xie; Scott D. Stull; Daniel Osterberg; Jason Reece; Jian Li - Web page: https://patentgrep.com/patent/US20220037360A1 ## CPC - H10B 43/27: the channels comprising vertical portions, e.g. U-shaped channels - H10B 41/27: the channels comprising vertical portions, e.g. U-shaped channels - H10B 41/35: with a cell select transistor, e.g. NAND - H10B 43/50: characterised by the boundary region between the core and peripheral circuit regions - H10D 62/292: {Non-planar channels of IGFETs (resulting from the gate electrode dispositions, e.g. within trenches H10D64/512)} - H10P 14/27: {using selective deposition, e.g. simultaneous growth of monocrystalline and non-monocrystalline semiconductor materials} - H10P 50/283: {by chemical means} - H10W 20/056: {by filling conductive material into holes, grooves or trenches} - H10W 20/0698: {Local interconnections} - H10W 20/081: {by forming openings in the dielectric parts} - H10W 20/42: Vias, e.g. via plugs - H10W 20/43: Layouts of interconnections - H10B 43/10: characterised by the top-view layout - H10B: ELECTRONIC MEMORY DEVICES - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES - H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10 - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract A device comprises an array of elevationally-extending transistors and a circuit structure adjacent and electrically coupled to the elevationally-extending transistors of the array. The circuit structure comprises a stair step structure comprising vertically-alternating tiers comprising conductive steps that are at least partially elevationally separated from one another by insulative material. Operative conductive vias individually extend elevationally through one of the conductive steps at least to a bottom of the vertically-alternating tiers and individually electrically couple to an electronic component below the vertically-alternating tiers. Dummy structures individually extend elevationally through one of the conductive steps at least to the bottom of the vertically-alternating tiers. Methods are also disclosed. ## Claims ### Claim 1 A device comprising: an array of elevationally-extending transistors; and a circuit structure adjacent and electrically coupled to the elevationally-extending transistors of the array, the circuit structure comprising: a stair step structure comprising vertically-alternating tiers comprising conductive steps that are at least partially elevationally separated from one another by insulative material; operative conductive vias individually extending elevationally through one of the conductive steps at least to a bottom of the vertically-alternating tiers and which individually electrically couple to an electronic component below the vertically-alternating tiers; and dummy structures individually extending elevationally through one of the conductive steps at least to the bottom of the vertically-alternating tiers. ### Claim 2 (depends on 1) The device of claim 1 wherein the dummy structures are individually conductive top-to-bottom through the vertically-alternating tiers. ### Claim 3 (depends on 1) The device of claim 1 wherein the operative conductive vias and the dummy structures are individually of the same peripheral size and peripheral shape. ### Claim 4 (depends on 1) The device of claim 1 wherein the operative conductive vias and the dummy structures individually comprise a conductive core and an insulative periphery. ### Claim 5 (depends on 4) The device of claim 4 wherein the conductive cores and the insulative peripheries in the operative conductive vias and the dummy structures individually extend top-to-bottom through the vertically-alternating tiers. ### Claim 6 (depends on 1) The device of claim 1 wherein the operative conductive vias individually extend elevationally through more than one of the conductive steps. ### Claim 7 (depends on 6) The device of claim 6 wherein the operative conductive vias individually extend elevationally through multiple of the conductive steps. ### Claim 8 (depends on 7) The device of claim 7 wherein the operative conductive vias individually extend elevationally through no more than two of the conductive steps. ### Claim 9 (depends on 8) The device of claim 8 wherein the operative conductive vias individually extend elevationally through equal surface areas of the two conductive steps through which the operative conductive vias elevationally extend. ### Claim 10 (depends on 1) The device of claim 1 wherein the dummy structures individually extend elevationally through more than one of the conductive steps. ### Claim 11 (depends on 10) The device of claim 10 wherein the dummy structures individually extending elevationally through multiple of the conductive steps. ### Claim 12 (depends on 7) The device of claim 7 wherein the dummy structures individually extend elevationally through no more than two of the conductive steps. ### Claim 13 (depends on 12) The device of claim 12 wherein the dummy structures individually extend elevationally through equal surface areas of the two conductive steps through which the dummy structures elevationally extend. ### Claim 14 (depends on 1) The device of claim 1 comprising operative conducting vias individually extending elevationally to and directly electrically coupling with conductive material of one of the conductive steps, individual of the operative conducting vias and individual of the operative conductive vias being directly electrically coupled to one another by an interconnect line that is above the stair step structure. ### Claim 15 (depends on 1) The device of claim 1 wherein one of the operative conductive vias and one of the dummy structures are side-by-side and extend elevationally through the same one of the conductive steps. ### Claim 16 (depends on 15) The device of claim 15 wherein the one operative conductive via and the one dummy structure also extend elevationally through another same one of the conductive steps. ### Claim 17 (depends on 1) The device of claim 1 wherein two of the dummy structures are side-by-side and extend elevationally through the same one of the conductive steps. ### Claim 18 (depends on 17) The device of claim 17 wherein the two dummy structures also extend elevationally through another same one of the conductive steps. ### Claim 19 (depends on 1) The device of claim 1 wherein one of the conductive steps comprises conductive material that extends into the array and which electrically couples to some of the transistors in the array, another of the conductive steps comprising conductive material that does not extend into the array and which does not electrically couple to any transistor in the array. ### Claim 20 (depends on 1) The device of claim 1 wherein the elevationally-extending transistors are memory cells. ### Claim 21 A device comprising: an array of elevationally-extending transistors; and a circuit structure adjacent and electrically coupled to the elevationally-extending transistors of the array, the circuit structure comprising: a first stair step structure and an adjacent second stair step structure individually comprising vertically-alternating tiers comprising first and second opposing sets of conductive steps, the conductive steps being at least partially elevationally separated from one another by insulative material in each of the first and second stair step structures; an elevationally-outer landing between the first stair step structure and the second stair step structure; operative conductive vias in each of the first and second stair step structures, the operative conductive vias individually extending elevationally through one of the conductive steps at least to a bottom of the vertically-alternating tiers of the respective first or second stair step structure and which individually electrically couple to an electronic component below the vertically-alternating tiers of the respective first or second stair step structure; first dummy structures in each of the first and second stair step structures, the first dummy structures individually extending elevationally through one of the conductive steps at least to the bottom of the vertically-alternating tiers of the respective first or second stair step structure; and a second dummy structure extending elevationally through the landing. ### Claim 22 (depends on 21) The device of claim 21 comprising multiple of the second dummy structures individually extending elevationally through the landing. ### Claim 23 A device comprising: an array of elevationally-extending transistors; and a circuit structure adjacent and electrically coupled to the elevationally-extending transistors of the array, the circuit structure comprising: a stair step structure comprising vertically-alternating tiers comprising first and second opposing flights of conductive steps, the conductive steps being at least partially elevationally separated from one another by insulative material; operative conductive vias individually extending elevationally through one of the conductive steps at least to a bottom of the vertically-alternating tiers and which individually electrically couple to an electronic component below the vertically-alternating tiers; first-flight-dummy structures individually extending elevationally through one of the first-flight conductive steps at least to the bottom of the vertically-alternating tiers; and second-flight-dummy structures individually extending elevationally through one of the second-flight conductive steps at least to the bottom of the vertically-alternating tiers. ### Claim 24 (depends on 23) The device of claim 23 wherein the first and second steps have the same total number of steps. ### Claim 25 (depends on 23) The device of claim 23 wherein the operative conductive vias extend elevationally only through the steps in one of the first or second flights and not in the other of the first and second flights. ### Claim 26 A device comprising: an array of elevationally-extending transistors comprising memory cells; and a circuit structure adjacent and electrically coupled to the elevationally-extending transistors of the array, the circuit structure comprising: a first stair step structure and an adjacent second stair step structure individually comprising vertically-alternating tiers comprising first and second opposing flights of conductive steps, the conductive steps being at least partially elevationally separated from one another by insulative material in each of the first and second stair step structures; operative conductive vias in each of the first and second stair step structures, the operative conductive vias individually extending elevationally through one of the conductive steps at least to a bottom of the vertically-alternating tiers of the respective first or second stair step structure and which individually electrically couple to an electronic component below the vertically-alternating tiers of the respective first or second stair step structure; first-flight-dummy structures in each of the first and second stair step structures, the first-flight-dummy structures individually extending elevationally through one of the first-flight conductive steps in the respective first or second stair step structure at least to the bottom of the vertically-alternating tiers of the respective first or second stair step structure; and second-flight-dummy structures in each of the first and second stair step structures, the second-flight-dummy structures individually extending elevationally through one of the second-flight conductive steps in the respective first or second stair step structure at least to the bottom of the vertically-alternating tiers of the respective first or second stair step structure.