# US 2022/0037352 A1 · Three-dimensional memory device with hydrogen-rich semiconductor channels

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 2022/0037352 A1
- Document ID: US20220037352A1
- Status: Published application
- Kind: A1
- Application number: 17/020,457
- Filed: 2020-09-14
- Published: 2022-02-03
- Earliest claimed: 2020-07-30
- Assignees: Yangtze Memory Technologies Co., Ltd.
- Applicants: Yangtze Memory Technologies Co., Ltd.
- Inventors: Kun Zhang; Wenxi Zhou; Zhiliang Xia; Zongliang Huo
- Web page: https://patentgrep.com/patent/US20220037352A1

## CPC

- H10B 43/27: the channels comprising vertical portions, e.g. U-shaped channels
- H10B 43/50: characterised by the boundary region between the core and peripheral circuit regions
- H10B 41/27: the channels comprising vertical portions, e.g. U-shaped channels
- H10B 41/30: characterised by the memory core region
- H10B 41/35: with a cell select transistor, e.g. NAND
- H10B 41/40: characterised by the peripheral circuit region
- H10B 43/30: characterised by the memory core region
- H10B 43/35: with cell select transistors, e.g. NAND
- H10B 43/40: characterised by the peripheral circuit region
- H10B: ELECTRONIC MEMORY DEVICES

## Abstract

Embodiments of 3D memory devices and methods for forming the same are disclosed. In an example, a 3D memory device includes a memory stack including interleaved stack conductive layers and stack dielectric layers, a semiconductor layer, a plurality of channel structures each extending vertically through the memory stack into the semiconductor layer, and an insulating structure extending vertically through the memory stack and including a dielectric layer doped with at least one of hydrogen or an isotope of hydrogen.

## Claims

### Claim 1

A three-dimensional (3D) memory device, comprising:
a memory stack comprising interleaved stack conductive layers and stack dielectric layers;
a semiconductor layer;
a plurality of channel structures each extending vertically through the memory stack into the semiconductor layer; and
an insulating structure extending vertically through the memory stack and comprising a dielectric layer doped with at least one of hydrogen or an isotope of hydrogen.

### Claim 2 (depends on 1)

The 3D memory device of claim 1, wherein an atomic percent of the at least one of hydrogen or an isotope of hydrogen in the dielectric layer is not greater than about 50%.

### Claim 3 (depends on 2)

The 3D memory device of claim 2, wherein the atomic percent of the at least one of hydrogen or an isotope of hydrogen in the dielectric layer is between about 1% and about 10%.

### Claim 4 (depends on 1)

The 3D memory device of claim 1, wherein the dielectric layer comprises silicon nitride.

### Claim 5 (depends on 1)

The 3D memory device of claim 1, wherein the insulating structure further comprises a first silicon oxide layer laterally between the dielectric layer and the stack conductive layers of the memory stack.

### Claim 6 (depends on 5)

The 3D memory device of claim 5, wherein the insulating structure further comprises a second silicon oxide layer, wherein the dielectric layer is laterally between the first and second silicon oxide layers.

### Claim 7 (depends on 5)

The 3D memory device of claim 5, wherein the insulating structure further comprises a polysilicon layer, wherein the dielectric layer is laterally between the first silicon oxide layer and the polysilicon layer.

### Claim 8 (depends on 1)

The 3D memory device of claim 1, wherein the insulating structure further comprises a silicon oxide cap at one end of the insulating structure.

### Claim 9 (depends on 1)

The 3D memory device of claim 1, wherein one end of the insulating structure is flush with a respective end of the dielectric layer.

### Claim 10 (depends on 1)

The 3D memory device of claim 1, wherein the semiconductor layer comprises one or more doped silicon layers.

### Claim 11 (depends on 1)

The 3D memory device of claim 1, wherein each of the channel structures comprises a memory film and a semiconductor channel doped with the at least one of hydrogen or an isotope of hydrogen.

### Claim 12 (depends on 11)

The 3D memory device of claim 11, wherein the semiconductor channel comprises polysilicon.

### Claim 13 (depends on 1)

The 3D memory device of claim 1, wherein the insulating structure extends laterally to separate the plurality of channel structures into a plurality of blocks.

### Claim 14 (depends on 1)

The 3D memory device of claim 1, further comprising a source contact in contact with the semiconductor layer, wherein the source contact and the insulating structure are on opposite sides of the semiconductor layer.

### Claim 15 (depends on 1)

The 3D memory device of claim 1, further comprising a source contact in contact with the semiconductor layer, wherein the source contact and the insulating structure are on a same side of the semiconductor layer.

### Claim 16

A three-dimensional (3D) memory device, comprising:
a memory stack comprising interleaved stack conductive layers and stack dielectric layers;
a semiconductor layer;
a plurality of channel structures each extending vertically through the memory stack into the semiconductor layer, wherein each of the channel structures comprises a memory film and a semiconductor channel doped with at least one of hydrogen or an isotope of hydrogen; and
an insulating structure extending vertically through the memory stack and comprising a dielectric layer.

### Claim 17 (depends on 16)

The 3D memory device of claim 16, wherein the dielectric layer is doped with the at least one of hydrogen or an isotope of hydrogen.

### Claim 18 (depends on 16)

The 3D memory device of claim 16, wherein the dielectric layer comprises silicon nitride.

### Claim 19

A method for forming a three-dimensional (3D) memory device, comprising:
forming a channel structure extending vertically through a memory stack into a semiconductor layer on a substrate, wherein the memory stack comprises interleaved stack conductive layers and stack dielectric layers; and
forming an insulating structure in an opening extending vertically through the memory stack and comprising a dielectric layer doped with at least one of hydrogen or an isotope of hydrogen.

### Claim 20 (depends on 19)

The method of claim 19, further comprising diffusing at least part of the at least one of hydrogen or an isotope of hydrogen to the channel structure.