# US 2022/0037338 A1 · Semiconductor structure and forming method thereof

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- Number: US 2022/0037338 A1
- Document ID: US20220037338A1
- Status: Published application
- Kind: A1
- Application number: 17/104,179
- Filed: 2020-11-25
- Published: 2022-02-03
- Earliest claimed: 2020-07-31
- Assignees: Semiconductor Manufacturing International (Shanghai) Corporation; Semiconductor Manufacturing International (Beijing) Corporation
- Applicants: Semiconductor Manufacturing International (Shanghai) Corporation; Semiconductor Manufacturing International (Beijing) Corporation
- Inventors: Nan WANG
- Web page: https://patentgrep.com/patent/US20220037338A1

## CPC

- H10B 10/12: {comprising a MOSFET load element}
- H10W 20/0698: {Local interconnections}
- H10D 30/601: {having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs (lightly doped source or drain extensions for TFTs H10D30/6715)}
- H10D 84/0149: {Manufacturing their interconnections or electrodes, e.g. source or drain electrodes}
- H10D 84/0158: {the components including FinFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10W 20/069: {by forming self-aligned vias or self-aligned contact plugs}
- H10W 20/42: Vias, e.g. via plugs
- H10D 30/6219: {characterised by the source or drain electrodes}
- H10D 30/797: {being in source or drain regions, e.g. SiGe source or drain}
- H10D 62/822: comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 84/83: of only insulated-gate FETs [IGFET]
- H10D 84/83125: {the IGFETs characterised by having shared source or drain regions}
- H10D 84/834: {comprising FinFETs}
- H10W 20/056: {by filling conductive material into holes, grooves or trenches}
- H10W 20/077: {on sidewalls or on top surfaces of conductors (H10W20/076 takes precedence)}
- H10B: ELECTRONIC MEMORY DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A semiconductor structure and a forming method thereof are provided. The method includes: providing a base having a gate structure, where there is a gate cap layer on the top of the gate structure, there is a source/drain doped region in the base on two sides of the gate structure, there is a bottom dielectric layer on the base, the base includes a shared contact region that is used for forming a shared contact plug, the source/drain doped region located in the shared contact region is used as a first source/drain doped region, and the remaining is used as a second source/drain doped region; forming, in a bottom dielectric layer, a first source-drain interconnection layer connected to the second source/drain doped region, and a source/drain cap layer located on the top of the first source-drain interconnection layer; forming, in the bottom dielectric layer, a second source-drain interconnection layer connected to the first source/drain doped region; forming a top dielectric layer covering the gate cap layer, the source/drain cap layer, the second source-drain interconnection layer, and the bottom dielectric layer; and forming, in the shared contact region, a shared contact plug running through the top dielectric layer and the gate cap layer. According to the present disclosure, difficulty in forming the shared contact plug is reduced, and the performance of the semiconductor structure is improved.

## Claims

### Claim 1

A forming method of a semiconductor structure, comprising:
providing a base, where:
a gate structure is formed on the base,
a gate cap layer is formed on a top of the gate structure,
a source/drain doped region is formed in the base on two sides of the gate structure,
a bottom dielectric layer is formed on the base at a side portion of the gate structure, and
the bottom dielectric layer covers side walls of the gate structure and the gate cap layer,
wherein a region that is located at the base and that is used for forming a shared contact plug electrically connecting the gate structure and the source/drain doped region is used as a shared contact region, the source/drain doped region located in the shared contact region is used as a first source/drain doped region, and the remaining source/drain doped region is used as a second source/drain doped region;
forming, in a bottom dielectric layer on a top of the second source/drain doped region, a first source-drain interconnection layer connected to the second source/drain doped region, and a source/drain cap layer located on a top of the first source-drain interconnection layer;
forming, in the bottom dielectric layer on a top of the first source/drain doped region, a second source-drain interconnection layer connected to the first source/drain doped region;
forming a top dielectric layer covering the gate cap layer, the source/drain cap layer, the second source-drain interconnection layer, and the bottom dielectric layer; and
forming, in the shared contact region, a shared contact plug running through the top dielectric layer and the gate cap layer, the shared contact plug electrically connecting the gate structure and the second source-drain interconnection layer.

### Claim 2 (depends on 1)

The forming method of a semiconductor structure according to claim 1, wherein after the source/drain cap layer is formed, the second source-drain interconnection layer is formed.

### Claim 3 (depends on 1)

The forming method of a semiconductor structure according to claim 1, wherein the step of forming the first source-drain interconnection layer and the source/drain cap layer comprises:
removing the bottom dielectric layer on the top of the second source/drain doped region, to from a first trench exposing the second source/drain doped region;
forming a first source-drain interconnection layer in the first trench, a top of the first source-drain interconnection layer being lower than a top of the bottom dielectric layer; and
forming the source/drain cap layer in a region surrounded by the bottom dielectric layer and the first source-drain interconnection layer.

### Claim 4 (depends on 3)

The forming method of a semiconductor structure according to claim 3, wherein the step of forming the first source-drain interconnection layer in the first trench comprises:
filling a conductive material into the first trench;
performing planarization on the conductive material using the top surface of the gate cap layer as a stop position; and
performing, after the planarization, back etching on the remaining conductive material in the first trench, the remaining conductive material after the back etching being used as the first source-drain interconnection layer.

### Claim 5 (depends on 1)

The forming method of a semiconductor structure according to claim 1, wherein the step of forming the second source-drain interconnection layer comprises:
removing the bottom dielectric layer on the top of the first source/drain doped region, to from a second trench exposing the first source/drain doped region; and
forming the second source-drain interconnection layer in the second trench.

### Claim 6 (depends on 5)

The forming method of a semiconductor structure according to claim 5, wherein the step of forming the second source-drain interconnection layer in the second trench comprises:
filling a conductive material into the second trench; and
performing planarization on the conductive material using the top surface of the gate cap layer as a stop position, the remaining conductive material in the second trench being used as the second source-drain interconnection layer.

### Claim 7 (depends on 3)

The forming method of a semiconductor structure according to claim 3, wherein the step of forming the first trench comprises: forming, on the bottom dielectric layer, a first mask layer having a first mask opening, the first mask opening exposing the bottom dielectric layer on the top of the second source/drain doped region;
etching, by using the first mask layer as a mask, the bottom dielectric layer exposed by the first mask opening, to form the first trench; and
removing the first mask layer after the first trench is formed.

### Claim 8 (depends on 5)

The forming method of a semiconductor structure according to claim 5, wherein the step of forming the second trench comprises:
forming, on the bottom dielectric layer, a second mask layer having a second mask opening, the second mask opening exposing the bottom dielectric layer on the top of the first source/drain doped region;
etching, using the second mask layer as a mask, the bottom dielectric layer exposed by the second mask opening, to form the second trench; and
removing the second mask layer after the second trench is formed.

### Claim 9 (depends on 1)

The forming method of a semiconductor structure according to claim 1, wherein a material of the gate cap layer is different from that of the source/drain cap layer.

### Claim 10 (depends on 1)

The forming method of a semiconductor structure according to claim 1, wherein:
the material of the gate cap layer comprises at least one of silicon nitride, silicon carbide, silicon carbon nitride, silicon oxycarbonitride, silicon oxynitride, boron nitride, or boron carbon nitride; and
the material of the source/drain cap layer comprises at least one of silicon nitride, silicon carbide, silicon carbon nitride, silicon oxycarbonitride, silicon oxynitride, boron nitride, or boron carbon nitride.

### Claim 11 (depends on 1)

The forming method of a semiconductor structure according to claim 1, wherein the step of forming the shared contact plug comprises:
etching the top dielectric layer and the gate cap layer in the shared contact region, to form a shared contact hole exposing the gate structure and the second source-drain interconnection layer; and
forming the shared contact plug in the shared contact hole.

### Claim 12 (depends on 1)

The forming method of a semiconductor structure according to claim 1, wherein:
in the step of providing the base, the gate structure extends in a first direction and is arranged in parallel in a second direction, the first direction is perpendicular to the second direction, and a spacer is formed on the side walls of gate structure and the gate cap layer; and
in the step of forming the shared contact plug, in the second direction, the shared contact plug is isolated from the adjacent source/drain cap layer through the spacer.

### Claim 13 (depends on 1)

The forming method of a semiconductor structure according to claim 1, wherein:
in the step of providing the base, the gate structure extends in a first direction and is arranged in parallel in a second direction, where the first direction is perpendicular to the second direction, and a spacer is formed on the side walls of the gate structure and the gate cap layer; and
the forming method further comprises: forming a gate plug in the top dielectric layer and the gate cap layer located on the top of the gate structure, wherein in the second direction, the gate plug is isolated from the adjacent second source-drain interconnection layer through the spacer.

### Claim 14 (depends on 1)

The forming method of a semiconductor structure according to claim 1, wherein the semiconductor structure is a static random-access memory (SRAM) device.

### Claim 15

A semiconductor structure, comprising:
a base, comprising:
a gate structure formed on the base,
a gate cap layer formed on a top of the gate structure,
a source/drain doped region formed in the base on two sides of the gate structure, and
a bottom dielectric layer formed on the base at a side portion of the gate structure, the bottom dielectric layer covering side walls of the gate structure and the gate cap layer,
wherein a region that is located at the base and that is used for forming a shared contact plug electrically connecting the gate structure and the source/drain doped region is used as a shared contact region, the source/drain doped region located in the shared contact region is used as a first source/drain doped region, and the remaining source/drain doped region is used as a second source/drain doped region;
a first source-drain interconnection layer, located in a bottom dielectric layer on a top of the second source/drain doped region and connected to the second source/drain doped region, a top of the first source-drain interconnection layer being lower than a top of the gate cap layer;
a source/drain cap layer, located at a region surrounded by the top of the first source-drain interconnection layer and the bottom dielectric layer;
a second source-drain interconnection layer, running through the bottom dielectric layer on the top of the first source/drain doped region; and
a top dielectric layer, covering the gate cap layer, the source/drain cap layer, the second source-drain interconnection layer, and the bottom dielectric layer.

### Claim 16 (depends on 15)

The semiconductor structure according to claim 15, wherein a material of the gate cap layer is different from that of the source/drain cap layer.

### Claim 17 (depends on 15)

The semiconductor structure according to claim 15, wherein:
the material of the gate cap layer comprises at least one of silicon nitride, silicon carbide, silicon carbon nitride, silicon oxycarbonitride, silicon oxynitride, boron nitride, or boron carbon nitride; and
the material of the source/drain cap layer comprises at least one of silicon nitride, silicon carbide, silicon carbon nitride, silicon oxycarbonitride, silicon oxynitride, boron nitride, or boron carbon nitride.

### Claim 18 (depends on 15)

The semiconductor structure according to claim 15, wherein the semiconductor structure is a static random-access memory (SRAM) device.