# US 2022/0037331 A1 · Method for preparing semiconductor device structure with air gap

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- Number: US 2022/0037331 A1
- Document ID: US20220037331A1
- Status: Published application
- Kind: A1
- Application number: 17/503,662
- Filed: 2021-10-18
- Published: 2022-02-03
- Earliest claimed: 2019-10-16
- Assignees: Nanya Technology Corporation
- Applicants: Nanya Technology Corporation
- Inventors: CHIN-TE KUO
- Web page: https://patentgrep.com/patent/US20220037331A1

## CPC

- H10B 12/37: {the capacitor being at least partially in a trench in the substrate}
- H10B 12/056: {the transistor being a FinFET}
- H10B 12/36: {the transistor being a FinFET}
- H10B 12/485: {Bit line contacts}
- H10B 12/488: {Word lines}
- H10D 84/0158: {the components including FinFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/834: {comprising FinFETs}
- H10W 10/014: {using trench refilling with dielectric materials, e.g. shallow trench isolations}
- H10W 10/021: {of air gaps}
- H10W 10/17: formed using trench refilling with dielectric materials, e.g. shallow trench isolations
- H10W 10/20: Air gaps
- H10B: ELECTRONIC MEMORY DEVICES
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A method for preparing a semiconductor device structure includes forming a first fin structure and a second fin structure over a semiconductor substrate, forming an isolation structure over the semiconductor substrate, partially removing the first fin structure and the second fin structure to form a recessed portion of the first fin structure and a recessed portion of the second fin structure, epitaxially growing a first source/drain (S/D) structure over the recessed portion of the first fin structure and a second S/D structure over the recessed portion of the second fin structure, partially removing the isolation structure through the first opening to form a second opening, and forming a contact etch stop layer (CESL) over the first S/D structure and the second S/D structure such that an air gap is formed and sealed in the first opening and the second opening.

## Claims

### Claim 1

A method for preparing a semiconductor device structure, comprising:
forming a first fin structure and a second fin structure over a semiconductor substrate;
forming an isolation structure over the semiconductor substrate, wherein the first fin structure and the second fin structure protrude from the isolation structure;
partially removing the first fin structure and the second fin structure to form a recessed portion of the first fin structure and a recessed portion of the second fin structure;
epitaxially growing a first source/drain (S/D) structure over the recessed portion of the first fin structure and a second S/D structure over the recessed portion of the second fin structure, wherein the first S/D structure is separated from the second S/D structure by a first opening;
partially removing the isolation structure through the first opening to form a second opening; and
forming a contact etch stop layer (CESL) over the first S/D structure and the second S/D structure such that an air gap is formed and sealed in the first opening and the second opening.

### Claim 2 (depends on 1)

The method for preparing a semiconductor device structure of claim 1, wherein a top surface and a sidewall of the recessed portion of the first fin structure protrude from the isolation structure before the first S/D structure is epitaxially grown.

### Claim 3 (depends on 1)

The method for preparing a semiconductor device structure of claim 1, wherein a width of the first opening increases from a top portion of the first opening to a bottom portion of the first opening, and a width of the second opening decreases from a top portion of the second opening to a bottom portion of the second opening.

### Claim 4 (depends on 1)

The method for preparing a semiconductor device structure of claim 1, wherein a sidewall of the isolation structure is exposed in the second opening.

### Claim 5 (depends on 4)

The method for preparing a semiconductor device structure of claim 4, wherein the CESL extends into the first opening and the second opening, and the sidewall of the isolation structure is covered by the CESL.

### Claim 6 (depends on 1)

The method for preparing a semiconductor device structure of claim 1, further comprising:
forming a first word line and a second word line across the first fin structure and the second fin structure, wherein the first S/D structure, the second S/D structure, and the air gap are between the first word line and the second word line; and
epitaxially growing a third S/D structure over another recessed portion of the first fin structure, wherein the first word line is between the first S/D structure and the third S/D structure, and the third S/D structure is electrically connected to a deep trench capacitor.

### Claim 7 (depends on 1)

The method for preparing a semiconductor device structure of claim 1, further comprising:
removing a portion of the CESL over the first S/D structure; and
forming a bit line contact over the first S/D structure, wherein the first S/D structure is electrically connected to a bit line through the bit line contact.