# US 2022/0037320 A1 · Semiconductor structure and method of manufacturing the same

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- Number: US 2022/0037320 A1
- Document ID: US20220037320A1
- Status: Published application
- Kind: A1
- Application number: 16/945,342
- Filed: 2020-07-31
- Published: 2022-02-03
- Earliest claimed: 2020-07-31
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company Ltd.
- Inventors: WEI-LUN CHEN
- Web page: https://patentgrep.com/patent/US20220037320A1

## CPC

- H10D 84/853: {comprising FinFETs}
- H10D 84/0167: {Manufacturing their channels}
- H10D 84/0172: {Manufacturing their gate conductors}
- H10D 84/0188: {Manufacturing their isolation regions}
- H10D 84/0193: {the components including FinFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 88/00: Three-dimensional [3D] integrated devices
- H10D 88/01: {Manufacture or treatment}
- B82Y 10/00: Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
- H10D 62/121: {oriented parallel to substrates}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES

## Abstract

A semiconductor structure comprises a substrate and a fin extruding from the substrate along a first direction, wherein the fin comprises a first conductive type semiconductive layer over the substrate, a second conductive type semiconductive layer stacking over the first conductive type semiconductive layer along the first direction, and a dielectric layer sandwiched by the first conductive type semiconductive layer and the second conductive type semiconductive layer providing electrical isolation along the first direction between the first conductive type semiconductive layer and the second conductive type semiconductive layer.

## Claims

### Claim 1

A semiconductor structure, comprising:
a substrate; and
a fin extruding from the substrate along a first direction, wherein the fin comprises a first conductive type semiconductive layer over the substrate, a second conductive type semiconductive layer stacking over the first conductive type semiconductive layer along the first direction, and a dielectric layer sandwiched by the first conductive type semiconductive layer and the second conductive type semiconductive layer providing electrical isolation along the first direction between the first conductive type semiconductive layer and the second conductive type semiconductive layer.

### Claim 2 (depends on 1)

The semiconductor structure of claim 1, wherein the dielectric layer is made of a material with a dielectric constant from about 3 to about 25.

### Claim 3 (depends on 1)

The semiconductor structure of claim 1, wherein the fin has a trapezoidal or rectangular cross section in vertical direction.

### Claim 4 (depends on 1)

The semiconductor structure of claim 1, wherein at least 50% of the area of sidewall of the fin is corrugated.

### Claim 5 (depends on 1)

The semiconductor structure of claim 1, wherein the fin has a corrugated sidewall with a plurality of recesses and each recess has a diameter ranging from about 1 nrm to about 10 nm.

### Claim 6 (depends on 1)

The semiconductor structure of claim 1, wherein the dielectric layer has an oblate shape with narrower top and bottom than middle portion.

### Claim 7 (depends on 1)

The semiconductor structure of claim 1, wherein the dielectric layer has a gourd shape.

### Claim 8 (depends on 1)

The semiconductor structure of claim 1, wherein the first conductive type semiconductive layer in the fin has a rectangular vertical cross section, the dielectric layer in the fin has a trapezoidal vertical cross section, and the second conductive type semiconductive layer has a rectangular vertical cross section.

### Claim 9

A semiconductor structure, comprising;
a substrate;
a first conductive type Fin field effect transistor (FinFET) over the substrate;
a second conductive type FinFET stacking over the first conductive type FinFET along a first direction;
a dielectric layer providing isolation between the first conductive type FinFET and the second conductive type FinFET along the first direction; and
a conductive rail lining along the second conductive type FinFET and extending on a second direction perpendicular to the first direction.

### Claim 10 (depends on 9)

The semiconductor structure of claim 9, wherein the dielectric layer is made of a material with a dielectric constant from about 3 to about 25.

### Claim 11 (depends on 9)

The semiconductor structure of claim 9, wherein one of the first conductive type FinFET and the second conductive type FinFET comprises a p-channel layer adjacent to the dielectric layer.

### Claim 12 (depends on 11)

The semiconductor structure of claim 11, further comprising an inner spacer surrounding the p-channel layer.

### Claim 13 (depends on 11)

The semiconductor structure of claim 11, wherein the p-channel layer has a thickness between about 20 nm and about 80 nm.

### Claim 14 (depends on 9)

The semiconductor structure of claim 9, wherein the dielectric layer has a thickness from about 10 nm to about 30 nm and the second conductive type FinFET has a thickness from about 20 nm to about 150 nm.

### Claim 15 (depends on 9)

The semiconductor structure of claim 9, wherein the conductive rail comprises two dielectric portions and an isolation portion sandwiched by the both dielectric portions and; and the dielectric portions and the isolation portion correspond to the first conductive type FinFET, the second conductive type FinFET and the dielectric layer, respectively.

### Claim 16

A method of manufacturing a semiconductor structure, comprising:
providing a substrate; and
forming a fin structure over the substrate comprising stacking a first conductive type semiconductive layer, a dielectric layer and a second conductive type semiconductive layer along a first direction.

### Claim 17 (depends on 16)

The method of claim 16, wherein forming the fin structure further comprises etching the second conductive type semiconductive layer, etching the dielectric layer, and etching the first conductive type semiconductive layer.

### Claim 18 (depends on 17)

The method of claim 17, wherein before etching the dielectric layer, a sacrificial film is formed surrounding the second conductive type semiconductive layer; and before etching the first conductive type semiconductive layer, a sacrificial film is formed surrounding the second conductive type semiconductive layer and the dielectric layer.

### Claim 19 (depends on 16)

The method of claim 16, further comprising forming a conductive rail over a portion of the fin structure, wherein the conductive rail lines along the second conductive type semiconductive layer and extends on a second direction perpendicular to the first direction.

### Claim 20 (depends on 16)

The method of claim 16, wherein the dielectric layer is made of a material with a dielectric constant from about 3 to about 25.