# US 2022/0037291 A1 · Die stack with cascade and vertical connections

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- Number: US 2022/0037291 A1
- Document ID: US20220037291A1
- Status: Published application
- Kind: A1
- Application number: 17/502,287
- Filed: 2021-10-15
- Published: 2022-02-03
- Earliest claimed: 2018-05-31
- Assignees: Intel Corporation
- Applicants: Intel Corporation
- Inventors: Min-Tih Ted Lai; Florence R. Pon; Yuhong Cai; John G. Meyers
- Web page: https://patentgrep.com/patent/US20220037291A1

## CPC

- H10W 90/00: Package configurations
- H10W 72/0198: {batch processes}
- H10W 70/099: {Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers}
- H10W 72/073: {of die-attach connectors}
- H10W 72/075: {of bond wires}
- H10W 72/07552: {changes in structures or sizes}
- H10W 72/50: Bond wires
- H10W 72/521: {Structures or relative sizes of bond wires}
- H10W 72/823: {Interconnections through encapsulations, e.g. pillars through molded resin on a lateral side a chip}
- H10W 72/884: {Die-attach connectors and bond wires}
- H10W 72/9413: {on encapsulations}
- H10W 74/00: Encapsulations, e.g. protective coatings
- H10W 74/019: {using temporary auxiliary substrates (H10W74/017 takes precedence)}
- H10W 90/24: at least one of the stacked chips being laterally offset from a neighbouring stacked chip, e.g. chip stacks having a staircase shape
- H10W 90/291: {characterised by containers, encapsulations, or other housings for the stacked chips}
- H10W 90/732: {between stacked chips}
- H10W 90/752: {between stacked chips}
- H10W 90/754: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

An electronic assembly includes a plurality of electronic die arranged into shingles, each shingle having a multiple offset stacked die coupled by cascading connections. Each shingle is arranged in a stack of shingles with alternate shingles having die stacked in opposite directions and offset in a zigzag manner to facilitate vertical electrical connections from a top of the electronic assembly to a bottom die of each shingle.

## Claims

### Claim 1

An electronic assembly, comprising:
a first shingle having multiple stacked offset die coupled via wirebonds on a top side and a first end of the first shingle;
a second shingle stacked on the first shingle having multiple stacked offset die coupled via wirebonds on a top side and a first end of the second shingle opposite the first end of the first shingle;
an electrical redistribution layer over the top side of the second shingle; and
multiple conductive vertical connections directly coupled between the redistribution layer and only one die in each of the first and second shingles.

### Claim 2 (depends on 1)

The electronic assembly of claim 1, wherein each shingle comprises at least four dies.

### Claim 3 (depends on 1)

The electronic assembly of claim 1, wherein the multiple conductive vertical connections include wirebond connections.

### Claim 4 (depends on 1)

The electronic assembly of claim 1, wherein the conductive vertical connections include through mold vias.

### Claim 5 (depends on 1)

The electronic assembly of claim 1, further comprising a mold surrounding the conductive vertical connections between the redistribution layer and the shingles.

### Claim 6

An electronic assembly comprising:
a plurality of electronic die arranged into shingles, each shingle having a multiple offset stacked die coupled by cascading connections; and
a plurality of direct conductive vertical connections only between the bottom die of each shingle to a top surface of an overmold of the electronic assembly.

### Claim 7 (depends on 6)

The electronic assembly of claim 6, wherein the cascading connections include wirebond connections.

### Claim 8 (depends on 6)

The electronic assembly of claim 6, further comprising an electrical redistribution layer over the top surface of the overmold.

### Claim 9 (depends on 6)

The electronic assembly of claim 6, wherein the multiple conductive vertical connections include wirebond connections.

### Claim 10 (depends on 6)

The electronic assembly of claim 6, wherein the conductive vertical connections include through mold vias.

### Claim 11

An electronic assembly comprising:
a plurality of electronic die arranged into shingles, each shingle having a multiple offset stacked die coupled by cascading connections, the shingles arranged in a stack of shingles;
a plurality of direct conductive vertical connections only between the bottom die of each shingle to a top surface of an overmold of the electronic assembly;
wherein a shingle offset between shingles decreases with increasing height of the stack of shingles.

### Claim 12 (depends on 11)

The electronic assembly of claim 11, wherein the stack of shingles includes four stacked shingles.

### Claim 13 (depends on 12)

The electronic assembly of claim 12, wherein each shingle comprises at least four dies.

### Claim 14 (depends on 13)

The electronic assembly of claim 13, wherein the cascading connections include wirebond connections.

### Claim 15 (depends on 11)

The electronic assembly of claim 11, further comprising an electrical redistribution layer over the top surface of the overmold.

### Claim 16 (depends on 11)

The electronic assembly of claim 11, wherein the multiple conductive vertical connections include wirebond connections.

### Claim 17 (depends on 11)

The electronic assembly of claim 11, wherein the conductive vertical connections include through mold vias.